Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-166 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PSIGNB __m128i _mm_sign_epi8 (__m128i a, __m128i b)
PSIGNW __m64 _mm_sign_pi16 (__m64 a, __m64 b)
PSIGNW __m128i _mm_sign_epi16 (__m128i a, __m128i b)
PSIGND __m64 _mm_sign_pi32 (__m64 a, __m64 b)
PSIGND __m128i _mm_sign_epi32 (__m128i a, __m128i b)
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS or GS segments.
(128-bit operations only) If not aligned on 16-byte boundary,
regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#UD If CR0.EM = 1.
(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.
If CPUID.SSSE3(ECX bit 9) = 0.
#NM If TS bit in CR0 is set.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#AC(0) (64-bit operations only) If alignment checking is enabled and
unaligned memory reference is made while the current privilege
level is 3.
Real Mode Exceptions
#GP(0) If any part of the operand lies outside of the effective address
space from 0 to 0FFFFH.
(128-bit operations only) If not aligned on 16-byte boundary,
regardless of segment.
#UD (128-bit operations only) If CR0.EM = 1. If CR4.OSFXSR(bit 9)
= 0.
If CPUID.SSSE3(ECX bit 9) = 0.
#NM If TS bit in CR0 is set.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
Virtual 8086 Mode Exceptions
Same exceptions as in Real Address Mode.
#PF(fault-code) If a page fault occurs.
#AC(0) (64-bit operations only) If alignment checking is enabled and
unaligned memory reference is made.