Intel Xeon Processor Specification Update

48 Intel
®
Xeon
®
Processor Specification Update
Errata
P74 Machine check exceptions may not update Last-Exception Record MSRs
(LERs)
Problem: The Last-Exception Record MSRs (LERs) may not get updated when machine check exceptions
(MCE) occur.
Implication: When this erratum occurs, the LER may not contain information relating to the MCE. They will
contain information relating to the exception prior to the MCE.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
P75 Stores to page tables may not be visible to page walks for subsequent loads
without serializing or invalidating the page table entry
Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger
memory access may not get data from a programmatically older store to the page table entry if
there is not a fencing operation or page translation invalidate operation between the store and the
younger memory access. Refer to the IA-32 Intel
®
Architecture Software Developer’s Manual for
the correct way to update page tables. Software that conforms to the IA-32 Intel
®
Architecture
Software Developer’s Manual will operate correctly.
Implication: If the guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual are not followed,
stale data may be loaded into the processor's translation lookaside buffer (TLB) and used for
memory operations. This erratum has not been observed with any commercially available software.
Workaround: The guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual should be followed.
Status: For the steppings affected, see the Summary Table of Changes.
P76 A timing marginality in the Arithmetic Logic Unit (ALU) may cause
indeterminate behavior
Problem: A timing marginality may exist in the clocking of the ALU which leads to a slowdown in the speed
of the circuit’s operation. This could lead to incorrect behavior of the ALU.
Implication: When this erratum occurs, unpredictable application behavior and/or system hang may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
P77 With Trap Flag (TF) asserted, FP instruction that triggers an unmasked FP
exception may take single step trap before retirement of instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for
external events to occur, including a transition to a lower power state. When resuming from the
lower power state, it may be possible to take the single step trap before the execution of the original
FP instruction completes.
Implication: A Single Step trap will be taken when not expected.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
P78 PDE/PTE loads and continuous locked updates to the same cache line may
cause a system livelock
Problem: In a multiprocessor configuration, if one processor is continuously doing locked updates to a cache
line that is being accessed by another processor doing a page table walk, the page table walk may
not complete.