Intel Xeon Processor Specification Update

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Intel

Xeon

Processor Specification Update 29

Errata

Implication: When this erratum occurs, data corruption may occur.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Table of Changes.

P9 Memory type of the load lock different from its corresponding store unlock

Problem: A use-once protocol is employed to ensure that the processor in a multi-agent system may access

data that is loaded into its cache on a RFO operation at least once before it is snooped out by

another agent. This protocol is necessary to avoid a multi-agent livelock scenario in which the

processor cannot gain ownership of a line and modify it before that data is snooped out by another

agent. In the case of this erratum, split load lock instructions incorrectly trigger the use-once

protocol. A load lock operation accesses data that splits across a page boundary with both pages of

WB memory type. The use-once protocol activates and the memory type for the split halves get

forced to UC. Since use-once does not apply to stores, the store unlock instructions go out as WB

memory type. The full sequence on the bus is: locked partial read (UC), partial read (UC), partial

write (WB), locked partial write (WB). The use-once protocol should not be applied to load locks.

Implication: When this erratum occurs, the memory type of the load lock will be different than the memory type

of the store unlock operation. This behavior (load locks and store unlocks having different memory

types) does not introduce any functional failures such as system hangs or memory corruption.

Workaround: None at this time.

Status: For the steppings affected, see the Summary Table of Changes.

P10 Machine check architecture error reporting and recovery may not work as

expected

Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the

situations described below, the processor does not report and/or recover from the error(s) as

intended.

• When a transaction is deferred during the snoop phase and subsequently receives a Hard

Failure response, the transaction should be removed from the bus queue so that the processor

may proceed. Instead, the transaction is not properly removed from the bus queue, the bus

queue is blocked, and the processor will hang.

• When a hardware prefetch results in an uncorrectable tag error in the L2 cache,

MC0_STATUS.UNCOR and MC0_STATUS.PCC are set but no machine check exception

(MCE) is signaled. No data loss or corruption occurs because the data being prefetched has not

been used. If the data location with the uncorrectable tag error is subsequently accessed, an

MCE will occur. However, upon this MCE, or any other subsequent MCE,.the information for

that error will not be logged because MC0_STATUS.UNCOR has already been set and the

MCA status registers will not contain information about the error which caused the MCE

assertion but instead will contain information about the prefetch error event.

• When the reporting of errors is disabled for machine check architecture (MCA) Bank 2 by

setting all MC2_CTL register bits to 0, uncorrectable errors should be logged in the

IA32_MC2_STATUS register but no machine-check exception should be generated.

Uncorrectable loads on bank 2, which would normally be logged in the IA32_MC2_STATUS

• When one half of a 64 byte instruction fetch from the L2 cache has an uncorrectable error and

the other 32 byte half of the same fetch from the L2 cache has a correctable error, the processor

will attempt to correct the correctable error but cannot proceed due to the uncorrectable error.

When this occurs the processor will hang.

• When an L1 cache parity error occurs, the cache controller logic should write the physical

address of the data memory location that produced that error into the IA32_MC1_ADDR