Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide
Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 11
8-10 Loop Clock Topology.........................................................................................121
8-11 IDSEL Sample Implementation Circuit .............................................................. 122
8-12 Manually-Operated Retention Latch Sensor .....................................................125
8-13 Attention Button Implementation .......................................................................126
8-14 Tri-State Buffer Circuit Example........................................................................128
8-15 Multiplexer Circuit Example............................................................................... 129
8-16 Single-Slot Parallel SMBus Circuit ....................................................................130
8-17 Reference Schematic for Single-Slot Parallel Mode .........................................131
8-18 Dual-Slot Parallel SMBus Circuit.......................................................................134
8-19 Reference Schematic for Dual-Slot Parallel Mode ............................................135
8-20 Four Slot Stutter Logic Implementation Example ..............................................137
8-21 Reference Schematic for Serial Mode...............................................................138
8-22 M66EN Isolation Switch Solution ......................................................................140
8-23 M66EN Diode Solution ...................................................................................... 141
9-1 Combination Host-Side/Device-Side IDE Cable Detection ...............................144
9-2 Connection Requirements for IDE Connector ...................................................145
9-3 Example Speaker Circuit...................................................................................146
9-4 PCI Bus Layout Example ..................................................................................146
9-5 Suggested USB Downstream Power Connection .............................................148
9-6 Intel
®
ICH3-S SMBus / SMLink Interface .........................................................149
9-7 Unified VCC3_3 Architecture ............................................................................150
9-8 High Power/Low Power Mixed VCC_SUSPEND/ VCC_CORE
Architecture .......................................................................................................151
9-9 RTCX1 and SUSCLK Relationship ...................................................................153
9-10 RTC Connection When Not Using Internal RTC ...............................................153
9-11 Example RTC External Circuitry........................................................................ 154
9-12 Platform LAN Connect ......................................................................................158
9-13 Point-to-Point Interconnect Guideline................................................................159
9-14 LAN_CLK Routing Example ..............................................................................160
9-15 Routing a 90-Degree Bend................................................................................161
9-16 Ground Plane Separation..................................................................................163
9-17 Intel
®
82562ET/EM Termination ....................................................................... 167
9-18 Critical Dimensions for Component Placement................................................. 167
9-19 Termination Plane .............................................................................................169
11-1 Power Delivery Example ...................................................................................173
11-2 Example of Good Plane Distribution to Power or Grounds of the Processor
Socket ...............................................................................................................177
11-3 Power Distribution Block Diagrams for DP System Motherboard ..................... 178
11-4 VRM VID Routing ..............................................................................................179
11-5 “Row” Pattern with Voltage Regulator Module ..................................................181
11-6 Simplified VRD Circuit Example ........................................................................182
11-7 “L” Pattern with Voltage Regulator Down .......................................................... 183
11-8 “Row” Pattern with Voltage Regulator Down..................................................... 183
11-9 Example Load Line Selection Circuit.................................................................184
11-10 CK408 / Processor Power Sequencing Requirement .......................................186
11-11 Power-Up Sequencing ......................................................................................187
11-12 Power-Down Sequencing..................................................................................187
11-13 Processor Filter Topology .................................................................................188
11-14 Filter Implementation 1: Using Discrete Resistor ..............................................189
11-15 Filter Implementation 2: No Discrete Resistor...................................................189