64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

14 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Summary Table of Changes
J74 X X No Fix Writing shared unaligned data that crosses a cache line without proper semaphores or
barriers may expose a memory ordering issue.
J75 X X No Fix Processor may hang during entry into No-Fill Mode or No-Eviction Mode.
J76 X X No Fix FPU Operand pointer may not be cleared following FINIT/FNINIT.
J77 X X No Fix L2 Cache ECC machine-check errors may be erroneously reported after an asynchronous
RESET# assertion.
J78 X X No Fix The IA32_MC0_STATUS/IA32_MC1_STATUS/ IA32_MC4_STATUS Overflow Bit is not set
when multiple un-correctable machine check errors occur at the same time.
J79 X X No Fix Debug Status Register (DR6) Breakpoint Condition Detected Flags may be set incorrectly.
Errata (Sheet 4 of 4)
No.
A-0/
0F41h
B-0/
0F49H
Plans Errata