64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 23
Errata
J20. Locks and SMC detection may cause the processor to temporarily hang
Problem: The processor may temporarily hang in an HT Technology enabled system, if one logical processor
executes a synchronization loop that includes one or more bus locks and is waiting for release by
the other logical processor. If the releasing logical processor is executing instructions that are
within the detection range of the self modifying code (SMC) logic, then the processor may be
locked in the synchronization loop until the arrival of an interrupt or other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop
making forward progress. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J21. Incorrect Debug Exception (#DB) may occur when a data breakpoint is set
on an FP instruction
Problem: The default Microcode Floating-Point Event Handler routine executes a series of loads to obtain
data about the FP instruction that are causing the FP event. If a data breakpoint is set on the
instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint
resulting in a Debug Exception.
Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP instruction.
Intel has not observed this erratum with any commercially available software or system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J22. xAPIC may not report some illegal vector error
Problem: The local xAPIC has an Error Status Register, which records all errors it detects. Bit 6 of this
register, the Receive Illegal Vector bit, is set when the local xAPIC detects an illegal vector in a
message that it receives. When an illegal vector error is received on the same internal clock that the
error status register is being written due to a previous error, bit 6 does not get set and illegal vector
errors are not flagged.
Implication: The xAPIC may not report some Illegal Vector errors when they occur at approximately the same
time as other xAPIC errors. The other xAPIC errors will continue to be reported.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J23. Enabling No-Eviction Mode (NEM) may prevent the operation of the second
logical processor in a Hyper-Threading Technology enabled Boot Strap
Processor (BSP)
Problem: In an HT Technology enabled system, when NEM is enabled by setting Bit 0 of MSR 080h
(IA32_BIOS_CACHE_AS_RAM), the second logical processor associated with the BSP may fail
to wake up from “Wait-for-SIPI” state.
Implication: In an HT Technology enabled system, the second logical processor associated with the BSP may
not respond to SIPI. The OS will continue to operate but with one less logical processor than
expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.