Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 7
9.7.2.1 General Trace Routing Considerations .............................. 161
9.7.2.2 Trace Geometry and Length...............................................162
9.7.2.3 Signal Isolation ...................................................................162
9.7.2.4 Power and Ground Connections.........................................162
9.7.2.5 General Power and Ground Plane Consideration .............. 163
9.7.2.6 Board Design ......................................................................164
9.7.2.7 Common Physical Layout Issues........................................164
9.7.3 Intel
®
82562ET/EM Guidelines.........................................................166
9.7.3.1 Guidelines for Intel
®
82562ET/EM Component Placement 166
9.7.3.2 Crystals and Oscillators ......................................................166
9.7.3.3 Intel
®
82562ET/EM Termination Resistors .........................167
9.7.4 Critical Dimensions...........................................................................167
9.7.5 Terminating Unused Connections ....................................................169
10 Debug Tools .............................................................................................................171
10.1 Logic Analyzer Interface (LAI) ...........................................................................171
10.2 Mechanical Considerations ...............................................................................171
10.3 Electrical Considerations...................................................................................171
11 Platform Power Delivery Guidelines ..............................................................173
11.1 Customer Reference Board Power Delivery .....................................................173
11.1.1 12 V ..................................................................................................174
11.1.2 Processor Core Voltage ...................................................................174
11.1.3 2.5 V .................................................................................................174
11.1.4 1.25 V ...............................................................................................174
11.1.5 1.8 V .................................................................................................174
11.1.6 1.2 V .................................................................................................175
11.1.7 5 VSB ...............................................................................................175
11.1.8 3.3 VSB ............................................................................................175
11.1.9 1.8 VSB ............................................................................................175
11.1.10 Power Summary...............................................................................175
11.2 Processor Power Distribution Guidelines ..........................................................176
11.2.1 Processor Power Requirements.......................................................176
11.2.1.1 Multiple Voltages ................................................................176
11.2.1.2 Voltage Tolerance...............................................................176
11.2.2 Power Delivery Layout Requirements ..............................................176
11.2.3 Voltage Regulator Requirements .....................................................178
11.2.3.1 Input Voltages and Currents ............................................... 178
11.2.3.2 Power Good Output (PWRGD)...........................................178
11.2.3.3 Fault Protection...................................................................179
11.2.3.4 VID Routing and Enable Logic............................................179
11.2.4 VR Module 9.1 Recommendations...................................................180
11.2.5 VR Down Recommendations ...........................................................182
11.2.5.1 VRD Placement ..................................................................182
11.2.5.2 Loadline Selection Circuitry ................................................184
11.2.5.3 VRD Circuit Implementation ...............................................185
11.2.6 Voltage Sequencing .........................................................................186
11.2.7 VCCA, VCCIOPLL, and VSSA Filter Specifications .........................188
11.2.8 Power Planes ................................................................................... 190
11.2.9 Processor Decoupling ...................................................................... 191
11.2.9.1 High-Frequency Decoupling ...............................................191
11.2.9.2 Bulk Decoupling..................................................................192