Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 223
High-Speed Design Concerns
Part 1 Solution: By definition, the DSTBN0# signal 5-inch route already includes the PLC and SI
motherboard trace components. The PLC and SI values are determined for DSTBN0# and
DSTBP0# using Equation 12-3 and Equation 12-4.
DSTBN0#
Processor PLC
= Maximum in Group
Processor Package Length
– DSTBN0#
Processor Package Length
= 0.578 inch - 0.208 inch= 0.370 inch
DSTBN0#
SI Adj
= 0.78 * DSTBN0#
Processor PLC
= 0.78 * 0.370 inch = 0.289 inch
DSTBP0#
Processor PLC
= Maximum in Group
Processor Package Length
– DSTBP0#
Processor Package Length
= 0.578 inch - 0.134 inch= 0.444 inch
DSTBP0#
SI Adj
= 0.78 * DSTBP0#
Processor PLC
= 0.78 * 0.444 inch = 0.346 inch
The DSTBP0# Processor 0/Processor 1 motherboard lengths are calculated using Equation 12-10.
DSTBP0#
Processor 0 to Processor 1 PCB Length
= DSTBP0#
Processor 0 to Processor 1 PCB Length
– DSTBN0#
Processor PLC
– DSTBN0#
SI Adj
+ DSTBP0#
Processor PLC
+ DSTBP0#
SI Adj
= 5.000 – 0.370 – 0.289 + 0.444 + 0.346 = 5.131 inches
Since the system bus data signals must be length matched within ± 25 mils between components,
the DSTBP0# Processor 0/Processor 1 motherboard length is 5.131 ± 0.025 inch.