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Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2 Design Guidelines

ManualsBrandsIntel ManualsOther64-bit Intel Xeon Processor 3.20E GHz, 2M Cache, 800 MHz FSB
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Output Voltage Requirements
10 Voltage Regulator Module (VRM) and Enterprise Voltage
Regulator-Down (EVRD) 10.2 Design Guidelines
baseboard temperatures. This includes voltage regulator layout, processor fan selection, ambient
temperature, chassis configuration, etc. To avoid heat related failures, baseboards should be
validated for thermal compliance under the envelope of system operating conditions. It is proposed
that the voltage regulator thermal protection be implemented for all designs (Section 6.2).
The maximum load current represents the maximum peak current that the processor is capable of
drawing. It is the maximum current the VRM/EVRD must be electrically designed to support
without tripping any protection circuitry.
2.2 Load Line Definitions - REQUIRED
The following load line contains static and transient voltage regulation data as well as maximum
and minimum voltage levels. It is recommended that the regulator’s differential remote sense point
for the processor’s voltage regulator be located at the center of the processor’s socket cavity.
The upper and lower load lines represent the allowable range of voltages that must be presented to
the processor. The voltage must never exceed these boundaries for proper operation of the
processor.
Figure 2-2 shows the load line voltage offsets and current levels based on the VID specifications
for the core regulator.
The encoding in Table 2-1 for the load lines is valid for the range of load current from 0 A to
150 A. The Load Line 0 (LL0) and Load Line 1 (LL1) control signals from Section 3.4, form a
2-bit load line selection and will be used to configure the Vcc VRM/EVRD to supply the proper
load lines for the processors. For implementation of LL0 and LL1 on the baseboard refer to the
appropriate platform design guidelines.
Figure 2-2. VRM/EVRD 10.2 Socket Load Line
-0.230
-0.180
-0.130
-0.080
-0.030
0.020
0 25507510012515
Icc (A)
Vcc (V) (Offset from VID)
Vmin
Vmax