ITP700 Debug Port Design Guide

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ITP700 Debug Port Design Guide 9
How to Use This Document
This document has two primary roles in the design process. First and foremost, this document is a
location for recording all of the best-known methods relating to the design of an ITP700 based
scan chain in a target. Second, this document serves as the Intel Corporation communication of
Design Guide and In Target Probe (ITP) signal specifications for a given processor. The document
is structured to serve both purposes.
Chapters 1 and 2 describe the debug port implementation guidelines for a generic uniprocessor
(UP) and generic multiprocessor (MP) system, respectively.
Chapter 3, 4, and 5 contain the Electrical and Mechanical Specifications for the ITP700 DPA,
ITP700 LVDPA, and ITP700 Flex respectively. These chapters include the specifications of the
different types of ITP hardware IO under all drive levels as well as specifications under non-
standard current loads and pull-up voltages. This information can be helpful if designers would
like to know more about the characteristics of the ITP under non-standard operating conditions, or
would like to interpolate the effects of changing recommended implementations to meet other
design requirements. This Keepout-Volume (KOV) information in the Mechanical Requirements
section is also useful when designing a debug port onto a platform.
Chapters 6 and beyond describe implementation information specific to particular Intel
Corporation processor families. This information includes expected input and output voltage
characteristics of the ITP (when terminated in the method recommended by this Design Guide) as
well as processor-specific implementation details that are not consistent with the ‘generic’
implementation guidelines in Chapter 1 through Chapter 5. These chapters make reference to the
‘generic’ UP and MP routing guidelines found in Chapters 1 and 2.
The Appendices go into detail on certain advanced design topics that are not relevant to the other
sections of this document. Appendices also include Spice Models for the ITP and a Designer’s
Checklist for a schematic and layout review.
System designers should first familiarize themselves with the general implementation, routing, and
termination rules as defined in the UP or MP implementation guidelines chapters of this document
as applicable to their design. They should then review the specific chapter for the processor that
the system is being designed for. Note that some of the generic implementations may not be
applicable based on the content of the processor specific chapter. Any non-standard design topics
are described in the appendices of this document.