Intel Xeon Processor Specification Update

Intel
®
Xeon
®
Processor Specification Update 43
Errata
P54 STPCLK# signal assertion under certain conditions may cause a system
hang
Problem: The assertion of STPCLK# signal before a logical processor awakens from the “Wait-for-SIPI”
state for the first time, may cause a system hang. A processor supporting HT Technology may fail
to initialize appropriately, and may not issue a Stop Grant Acknowledge special bus cycle in
response to the second STPCLK# assertion.
Implication: When this erratum occurs in an HT Technology enabled system, it may cause a system hang.
Workaround: BIOS should initialize the second thread of the processor supporting HT Technology prior to
STPCLK# assertion. Additionally, it is possible for the BIOS to contain a workaround for this
erratum.
Status: For the steppings affected, see the Summary Table of Changes.
P55 Store to load data forwarding may result in switched data bytes
Problem: If in a short window, after an instruction that updates a segment register has executed but not yet
retired, there is a load occurring to an address that matches a recent previous store operation but the
data size is smaller than the size of the store, the resulting data forwarded from the store to the load
may have some of the lower bytes switched.
Implication: If this erratum occurs, the processor may execute with incorrect data.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
P56 ITP cannot continue single step execution after the first breakpoint
Problem: ITP will not continue in single step execution after the first software breakpoint. ITP is unable to
reset the resume flag (RF) bit in the EFLAGS register.
Implication: The processor will break at the instruction breakpoint address instead of single stepping.
Workaround: Execution after the break will continue if DR7 bit 1 (Global Breakpoint Enable) is manually
cleared.
Status: For the steppings affected, see the Summary Table of Changes.
P57 Parity error in the L1 cache may cause the processor to hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the
processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any
commercially available software.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
P58 The TCK input in the test access port (TAP) is sensitive to low clock edge
rates and prone to noise coupling onto TCK's rising or falling edges
Problem: TCK is susceptible to double clocking when low amplitude noise occurs on TCK edge, while it is
crossing the receiver's transition region. TAP failures tend to increase with increases in background
system noise.
Implication: This only impacts JTAG/TAP accesses to the processor. Other bus accesses are not affected.
Workaround: To minimize the effects of this issue, reduce noise on the TCK-net at the processor relative to
ground, and position TCK relative to BCLK to minimize the TAP error rate. Decreasing rise times
to under 800ps reduced the failure rate but does not stop all failures.