Intel Xeon Processor Specification Update

Intel

Xeon

Processor Specification Update 19

Mixed Steppings in DP Systems

NOTES:

1. Some of these processors are affected by errata, which may affect the features an MP system is able to support. See the

Table 1 for details on which processors are affected by these errata.

2. This Matrix also applies to the Intel

Xeon

Processor with 533 MHz Front Side Bus, Low Voltage Intel

Xeon

Processor,

Intel

Xeon

Processor with 1-MB L3 cache, and Intel

Xeon

Processor with 2-MB L3 cache.

3. This only applies to 0F25h stepping without L3 cache.

4. This only applies to 0F25h stepping with L3 cache.

Table 2. DP Platform Matrix for the Intel

Xeon

Processor

Signature/Core

Stepping

0F0Ah/C1 0F12h/D0 0F24h/B0 0F27h/C1 0F29h/D1 0F25h/M0

0F25h/M0

0F0Ah/C1 NI Note 1 X X X X X

0F12h/D0 Note 1 NI X X X X X

0F24h/B0 X X NI NI NI NI X

0F27h/C1 X X NI NI NI NI X

0F29h/D1 X X NI NI NI NI X

0F25h/M0 X X NI NI NI NI NI

0F29h/L0 X X NI NI NI NI X