Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

System Bus Routing Guidelines
76 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
The reference circuit contains a multiplexer device that uses the System Management Bus Present
(SM_PRT) signal to select between the system SMBus interfacing with the SMBus from the
motherboard’s thermal sensor versus the processor SMBus. The multiplexer will only select the
processor’s SMBus interface when an Intel Xeon processor with 512-KB L2 cache (Hi-Z SM_PRT
signal that goes high with the pull-up) is present, resulting in the IN[3:1] inputs driven high.
Installation of an Intel Xeon processor with 533 MHz system bus (Grounded SM_PRT signal)
results in the multiplexer selecting the motherboard thermal sensor to interface with the system
SMBus, resulting in the IN[3:1] inputs driven low.
Note that the SMBus address of the motherboard thermal sensor and processor thermal sensor are
configured identically to each other, transparent to Server Management software/firmware
regardless of which processor package type is installed. Both the processor and thermal sensor
inject current onto their three state address pins to determine their address. The thermal sensor does
this every time it does an A/D conversion. As a result, both devices should not share the same
address resistors.
Figure 5-11 shows a reference circuit similar to Figure 5-10. This circuit requires all of the
following thermal sensor properties be properly electrically isolated from the SMBus when the
sensor is disabled by the P-channel FET circuit. Refer to our thermal sensor datasheet
documentation to confirm these requirements:
The SCLK, SDATA, and ALRT# signals must exhibit a High-Z state. For example, high input
current due to backpowering of the device or unpredictable I/O logic behavior as a result of a
grounded VDD may prevent correct SMBus operation by pulling any of these signals to an
electrically low state.
Figure 5-10. Circuit Implementation for Hardware-Based SMBus Selection Using Mux
AA28
Y29
Y28
Y27 3
4
6
10
ADD1
ADD0
D-
D+
2
VDD
GND
GND
7
8
SM_VCC
Thermal
Sensor
Processor
Mux
15
14
12
11
STBY#
SCLK
SDATA
ALRT#
SM_VCC
2
5
13
S1B
S2B
S3B
20
7
11
S1A
S2A
S3A
AC28
AC29
AD28
AE4
19
8
9
IN1
IN2
IN3
SM_VCC
3
Vss
Vdd
D3
D2
D1
14
12
6
1
SM_CLK
SM_DAT
SM_ALERT#
Onboard
SMBUS
Signals
SM_TS1_A0
SM_TS1_A1
THERMDA
THERMDC
SM_CLK
SM_DAT
SM_ALERT#
SMB_PRT
Use any combination of
resistors for addresses