64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 43
—Intel
®
Xeon™ Processor with 800 MHz System Bus
S73 The base of an LDT (Local Descriptor Table) register may be
non-zero on a processor supporting Intel
®
Extended Memory 64
Technology (Intel
®
EM64T)
Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT
register may be non-zero.
Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected
behavior when accessing an LDT register using the null selector. There may be
no #GP fault in response to this access.
Workaround:None identified.
Status: For the steppings affected, see the Summary of Changes.
S74 Unaligned Page-Directory-Pointer (PDPTR) Base with 32-bit
mode PAE (Page Address Extension) paging may cause
processor to hang
Problem: When the MOV to CR0, CR3 or CR4 instructions are executed in legacy PAE
paging mode and software is using an unaligned PDPTR base the processor
may hang or an incorrect page translation may be used.
Implication: Software that is written according to Intel's alignment specification (32-byte
aligned PDPTR Base) will not encounter this erratum. Intel has not observed
this erratum with commercially available software. Systems may hang or
experience unpredictable behavior when this erratum occurs.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Changes.
S75 Memory ordering failure may occur with snoop filtering third-
party agents after issuing and completing a BWIL (Bus Write
Invalidate Line) or BLW (Bus Locked Write) transaction
Problem: Under limited circumstances, the processors may, after issuing and completing
a BWIL or BLW transaction, retain data from the addressed cache line in
shared state even though the specification requires complete invalidation. This
data retention may also occur when a BWIL transaction’s self-snooping yields
HITM snoop results.
Implication: A system may suffer memory ordering failures if its central agent incorporates
coherence sequencing which depends on a full self-invalidation of the cache
line associated with (1) BWIL and BLW transactions, or (2) all HITM snoop
results without regard to the transaction type and snoop results’ source.
Workaround:1. The central agent can issue a bus cycle that causes a cache line to be
invalidated (Bus Read Invalidate Line (BRIL) or BWIL transaction) in response
to a processor-generated BWIL (or BLW) transaction to insure complete
validation of the associated cache line. If there are no intervening processor-
originated transactions to that cache line, the central agent’s invalidating
snoop will get a clean snoop result. Or,
1.Snoop filtering central agents can:
a.Not use processor-originated BWIL or BLW transactions to update their
snoop filter information, or