Intel Xeon Processor MP Specification Update

16 Intel
®
Xeon
®
Processor MP Specification Update
Summary Tables of Changes
O26 XX
XX
No Fix Processor issues inconsistent transaction size attributes for
locked operations
O27 XX
XX
No Fix Multiple accesses to the same S-state L2 cache line and ECC
error combination may result in loss of cache coherence
O28 XX
XX
No Fix IA32_MC0_ADDR and IA32_MC0_MISC registers will contain
invalid or stale data following a data, address, or response parity
error
O29 XX
XX
No Fix Instruction pointer stored on stack may become invalid
O30 XX
XX
No Fix When the processor is in the system management mode (SMM),
debug registers may be fully writeable
O31 XFixedAssociated counting logic must be configured when using event
selection control (ESCR) MSR
O32 XX FixedLivelock may occur when bus parking is disabled
O33 XX
XX
No Fix CPUID function 2 may return incorrect cache size information
O34 XX
XX
No Fix CR2 may be incorrect or an incorrect page-fault error code may be
pushed onto stack after execution of an LSS instruction
O35 XX
XX
No Fix Hyper-Threading Technology enabled processors may hang in the
presence of extensive self-modifying code
O36 XX
XX
No Fix Global bit incorrectly set for secondary logical processors in ITLB
O37 XX FixedHardware prefetcher may cause stale data to be loaded into the
processor caches
O38 XX
XX
No Fix System may hang if a fatal cache error causes bus write line
(BWL) transaction to occur to the same cache line address as an
outstanding bus read line (BRL) or bus read-invalidate line (BRIL)
O39 XX
XX
No Fix Re-mapping the APIC base address to a value less than or equal
to 0xDC001000 may cause I/O and special cycle failure
O40 XFixedErroneous machine check error reported
O41 XX
XX
No Fix Processor does not flag #GP on non-zero write to certain MSRs
O42 XX
XX
No Fix Counting both L2 and L3 cache reference events may result in
undercount
O43 XX
XX
No Fix
Simultaneous assertion of A20M# and INIT# may result in
incorrect data fetch
O44 XFixedIncorrect Brand ID and Brand string
O45 XFixedCPUID instruction returns incorrect number of ITLB entries
O46 XX
XX
No Fix A write to APIC task priority register (TPR) that lowers priority may
seem to have not occurred
O47 XFixedProcessor does not respond to break requests from ITP
O48 X
XX
No Fix Erroneous BIST result found in EAX register after reset
O49 XFixedFalse data strobe glitch machine check error may occur when the
machine check handler is enabled
O50 X
XX
No Fix Processor may hang under certain frequencies and 12.5%
STPCLK# duty cycle
O51 X
X
Fixed BPM[5:3]# VIL does not meet specification
O52 X X X X Plan Fix STPCLK# signal assertion under certain conditions may cause a
system hang
Errata (Sheet 2 of 4)
No.
0F11h
/C0
0F22h/
A0
OF25h\/
B0
0F26h/
C0
Plans Errata