Intel Xeon Processor MP Specification Update

Intel

Xeon

Processor MP Specification Update 11

Mixed Steppings In MP Systems

Intel Corporation fully supports mixed steppings of Intel Xeon Processors MP. The following list

and processor matrix describes the requirements to support mixed steppings:

• Mixed steppings are only supported with processors that have identical family numbers as

indicated by the CPUID instruction. The Intel Xeon Processor MP is available with two

different Model numbers as indicated by the CPUID. Please refer to the “Table 2 for details

regarding inclusion of processors with mixed CPUID/Core steppings.

• While Intel has done nothing to specifically prevent processors operating at differing

frequencies from functioning within a multiprocessor system, there may be uncharacterized

errata that exist in such configurations. Intel does not support such configurations. In mixed

stepping systems, all processors must operate at identical frequencies (i.e., the highest

frequency rating commonly supported by all processors).

• While there are no known issues associated with the mixing of processors with differing cache

sizes in a multiprocessor system, and Intel has done nothing to specifically prevent such

system configurations from operating, Intel does not support such configurations since there

may be uncharacterized errata that exist. In mixed stepping systems, all processors must be of

the same cache size.

• While Intel believes that certain customers may wish to perform validation of system

configurations with mixed frequency or cache sizes, and that those efforts are an acceptable

option to our customers, customers would be fully responsible for the validation of such

configurations.

• Intel requires that the proper microcode update be loaded on each processor operating in a

multiprocessor system. Any processor that does not have the proper microcode update loaded

is considered by Intel to be operating out of specification.

• The workarounds identified in this and following specification updates must be properly

applied to each processor in the system. Certain errata are specific to the multiprocessor

environment and are identified in Table 2 found at the end of this section. Errata for all

processor steppings will affect system performance if not properly worked around. Also see

Table 1 section for additional details on which processors are affected by specific errata.

• In mixed stepping systems, the processor with the lowest feature-set, as determined by the

CPUID Feature Bytes, must be the bootstrap processor (BSP). In the event of a tie in

feature-set, the tie should be resolved by selecting the BSP as the processor with the lowest

stepping as determined by the CPUID instruction.

In the following processor matrix, “NI” indicates that there are currently no known issues

associated with mixing these steppings. A number indicates that a known issue has been identified

as listed in the table following the matrix. “X” indicates the processors cannot be mixed. A

multiple processor system using mixed processor steppings must assure that errata are addressed

appropriately for each processor.