Intel Xeon Processor Specification Update

Intel
®
Xeon
®
Processor Specification Update 25
Summary Table of Changes
P68 XNo FixModified cache line eviction from L2 cache may
result in write back of stale data
P69 XXXXXXXNo FixxAPIC may not report some illegal vector errors
P70 XXXXXXXNo FixIncorrect duty cycle is chosen when On-Demand
Clock Modulation is enabled in a processor
supporting Hyper-Threading Technology
P71 XXXXXXXPlan FixMemory aliasing of pages as uncacheable memory
type and write back (WB) may hang the system
P72 XXXPlan FixA timing marginality in the Instruction Decoder unit
may cause an unpredictable application behavior
and/or system hang
P73 XXXXXXXNo FixMissing Stop Grant Acknowledge special bus cycle
may cause a system hang
P74 XXXXXXXNo FixMachine check exceptions may not update
Last-Exception Record MSRs (LERs)
P75 XXXXXXXNo FixStores to page tables may not be visible to page
walks for subsequent loads without serializing or
invalidating the page table entry
P76 XXXPlan FixA timing marginality in the Arithmetic Logic Unit
(ALU) may cause indeterminate behavior
P77 XXXXXXXNo FixWith Trap Flag (TF) asserted, FP instruction that
triggers an unmasked FP exception may take
single step trap before retirement of instruction
P78 XXXXXXXNo FixPDE/PTE loads and continuous locked updates to
the same cache line may cause a system livelock
P79 XXXXXXXNo FixBranch Trace Store (BTS) and Precise Event
Based Sampling (PEBS) may update memory
outside the BTS/PREBS buffer
P80 XXXXXXXNo FixMemory Ordering Failure may occur with Snoop
Filtering Third-Party Agents after Issuing and
completing a BWIL (Bus Write Invalidate Line) or
BLW (Bus Locked Write) transaction
P81 XXXXXXXNo FixControl Register 2 (CR2) can be updated during a
REP MOVS/STOS instruction with Fast Strings
enabled
P82 XXXXXXXNo FixWriting the Local Vector Table (LVT)
when an Interrupt is Pending May Cause an
Unexpected Interrupt
P83 XXXXXXXNo FixThe Processor May Report a #TS Instead of a #GP
Fault
Errata (Sheet 4 of 4)
No.
C1/
0F0Ah
D0/
0F12h
B0/
0F24h
C1/
0F27h
D1/
0F29h
M0/
0F25h
L0/
0F29h
Plans Errata