Intel Xeon Processor MP Specification Update

18 Intel
®
Xeon
®
Processor MP Specification Update
Summary Tables of Changes
O76 XXXXNo FixBranch Trace Store (BTS) and Precise Event Based Sampling
(PEBS) may update memory outside the BTS/PREBS buffer
O77 XXXXNo FixMemory Ordering Failure may occur with Snoop Filtering
Third-Party Agents after issuing and completing a BWIL (Bus
Write Invalidate Line) or BLW (Bus Locked Write) transaction
O78 XXXXNo FixControl Register 2 (CR2) can be updated during a REP
MOVS/STOS instruction with Fast Strings enabled
O79 XXXXNo FixWriting the local vector table (LVT) when an interrupt is pending
may cause an unexpected interrupt
Specification Changes
No. SPECIFICATION CHANGES
None for this revision of the Specification Update
Specification Clarifications
No. SPECIFICATION CLARIFICATIONS
O1 Specification Clarification with respect to Time-Stamp Counter
Documentation Changes
No. DOCUMENTATION CHANGES
None for this revision of the Specification Update
Errata (Sheet 4 of 4)
No.
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0F22h/
A0
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B0
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C0
Plans Errata