Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
RESERVED28
RESERVED27
RESERVED26
RESERVED25
RESERVED24
RESERVED23
RESERVED22
RESERVED21
RESERVED20
RESERVED19
RESERVED16
RESERVED15
RESERVED14
RESERVED13
RESERVED12
RESERVED11
RESERVED10
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED3
RESERVED2
RESERVED1
RESERVED0
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
RESERVED17
RESERVED18
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
CLK_VIEW
GND28
TEST
+V3_3
39
Gigabit Ethernet Controller (Part 5)
Intel (R) 82545EM Gigabit Etherenet controller routing:
Pins A20, B18, M5 tie to GND
85
R1220 680
R1219
680
R1218
680
R1216
680
R1214
680
R1215
680
R1210 680
R1211
680
R1212
680
R1207
680
R1208
680
R1205
680
R1206
680
C374
0.01UF
C373
0.01UF
C372
0.01UF
C371
0.01UF
C370
0.01UF
C369
0.01UF
C368
0.01UF
C367
0.01UF
R1122
1K
A6
E7
M5
B18
A20
C6
B10
C11
A9
D10
B9
C9
D9
E9
E8
C8
A7
B7
E10
C7
D7
E6
B5
E5
C5
E4
C4
D5
D4
N2
M3
K20
K19
J20
J19
J5
J4
H1
G20
G19
F20
F19
F5
F4
A12
A11
W19
W15
W11
W7
W3
V2
U17
U13
U9
U5
R19
R2
R1
P11
P10
N17
N12
N11
N10
N9
M13
M12
M11
M10
M9
M8
M4
L19
P4
P1
P2
N5
P5
P3
A8
U3
R338
1K
R1209
680
R1213
680
R1217
680
1.0INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD
11/18/02