Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 17
Introduction
Introduction 1
This design guide documents Intel’s design recommendations for systems based on the Intel
®
Xeon™ processor with 512-KB L2 cache / Intel
®
Xeon™ processor with 533 MHz system bus and
the Intel
®
E7500/E7501 chipset. This guide is intended for E7500/E7501 chipset compatible
platforms. All new E7500 chipet platforms should use this document. Existing E7500 chipset-only
designs may still conform to the Intel
®
Xeon™ Processor with 512 KB L2 Cache and Intel
®
E7500
Chipset Platform Design Guide. In addition to providing motherboard design recommendations
(e.g., layout and routing guidelines), this document addresses system design issues (e.g., power
delivery).
Carefully follow the design information, board schematics, debug recommendations, and system
checklists provided in this document. These design guidelines have been developed to ensure
maximum flexibility for board designers while reducing the risk of board related issues.
Note that the guidelines recommended in this document are based on experience and simulation
work completed at Intel while developing Intel Xeon processor / E7500/E7501 chipset-based
systems.
Board designers may use the associated Intel schematics as a reference. While the schematics cover
a specific design implementation, the core schematics remain the same for most E7500/E7501
chipset-based platforms. The schematic set provides a reference schematic for each E7500/E7501
chipset component as well as common motherboard options. Additional flexibility is possible
through other permutations of these options and components.
1.1 Terminology
This section defines terminology used throughout the design guide.
Terminology Description
Aggressor A network that transmits a coupled signal to another network.
AGTL+ The processor system bus uses a bus technology called AGTL+, or Assisted
Gunning Transceiver Logic. AGTL+ buffers are open-drain, and require pull-up
resistors to provide the high logic level and termination. AGTL+ output buffers
differ from GTL+ buffers with the addition of an active pMOS pull-up transistor to
assist the pull-up resistors during the first clock of a low-to-high voltage
transition.
Asynchronous GTL+ Legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy
output signals (FERR# and IERR#) and non-AGTL+ signals (THERMTRIP# and
PROCHOT#) also utilize GTL+ output buffers. All of these signals follow the
same DC requirements as AGTL+ signals, however the outputs are not actively
driven high (during a logical 0 to 1 transition) by the processor (the major
difference between GTL+ and AGTL+). These signals do not have setup or hold
time specifications in relation to BCLK[1:0], and are therefore referred to as
“Asynchronous GTL+ Signals”. All of the Asynchronous GTL+ signals must be
asserted for at least two BCLKs for the processor to recognize them.
Bus Agent A component or group of components that, when combined, represent a single
load on the system bus.