64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

32 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Errata
BIOS provides only valid physical address ranges to the operating system, this erratum will not
occur.
Workaround: BIOS must provide valid physical address ranges to the operating system.
Status: For the steppings affected, see the Summary Table of Changes.
J52. IA32_MCi_STATUS MSR may improperly indicate that additional MCA
information may have been captured
Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the
IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR
and IA32_MCi_MISC MSRs were not properly captured.
Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and
IA32_MCi_MISC may not correspond to the reported machine-check error, even though the
ADDRV and MISCV are asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J53. With Trap Flag (TF) asserted, FP instruction that triggers an unmasked FP
exception may take single step trap before retirement of instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for
external events to occur, including a transition to a lower power state. When resuming from the
lower power state, it may be possible to take the single step trap before the execution of the original
FP instruction completes.
Implication: A Single Step trap will be taken when not expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J54. PDE/PTE loads and continuous locked updates to the same cache line may
cause a system livelock
Problem: In a multiprocessor configuration, if one processor is continuously doing locked updates to a cache
line that is being accessed by another processor doing a page table walk, the page table walk may
not complete.
Implication: Due to this erratum, the system may livelock until some external event interrupts the locked
update. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J55. Branch Trace Store (BTS) and Precise Event Based Sampling (PEBS) may
update memory outside the BTS/PEBS buffer
Problem: If the BTS/PEBS buffer is defined such that:
• The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum is not an
integer multiple of the corresponding record sizes
• BTS/PEBS absolute maximum is less than a record size from the end of the virtual address
space
• The record that would cross BTS/PEBS absolute maximum will also continue past the end of
the virtual address space