Intel Xeon Processor Specification Update

24 Intel
®
Xeon
®
Processor Specification Update
Summary Table of Changes
P47 XXXXXXXNo FixRe-mapping the APIC base address to a value less
than or equal to 0xDC001000 may cause I/O and
special cycle failure
P48 XXXXXNo FixErroneous BIST result found in EAX register after
reset
P49 XXX FixedProcessor does not flag #GP on non-zero write to
certain MSRs
P50 XXXXX XNo FixSimultaneous assertion of A20M# and INIT# may
result in incorrect data fetch
P51 XX FixedProcessor does not respond to break requests
from ITP
P52 XXX FixedGlitches on address and data strobe signals may
cause system shutdown
P53 XXXXXXXNo FixA write to an APIC Register Sometimes May
Appear to Have Not Occured
P54 XXXPlan FixSTPCLK# signal assertion under certain conditions
may cause a system hang
P55 XXXXPlan FixStore to load data forwarding may result in
switched data bytes
P56 XXXXPlan FixITP cannot continue single step execution after the
first breakpoint
P57 XXXXXXXNo FixParity error in the L1 cache may cause the
processor to hang
P58 XXXXXXXPlan FixThe TCK input in the test access port (TAP) is
sensitive to low clock edge rates and prone to
noise coupling onto TCK's rising or falling edges
P59 XXXXXXXNo FixDisabling a local APIC disables both logical
processor on a Hyper-Threading Technology
enabled processor
P60 XXXXXXXNo FixUsing STPCLK and executing code from very slow
memory could lead to a system hang
P61 X Plan Fix Simultaneous cache line eviction from L2 and L3
caches may result in the write back of stale data
P62 XXXXXXXNo FixThe state of the resume flag (RF flag) in a
task-state segment (TSS) may be incorrect
P63 XXXXNo FixChanges to CR3 register do not fence pending
instruction page
P64 XXXXXPlan FixSimultaneous page-faults at similar page offsets on
both logical processors of an Hyper-Threading
Technology enabled processor may cause
application failure
P65 XXXXXXXNo FixA 16-bit address wrap resulting from a near branch
(jump or call) may cause an incorrect address to be
reported to the #GP exception handler
P66 XXXXXXXNo FixLocks and SMC detection may cause the
processor to temporarily hang
P67 XXXXXXXNo FixIncorrect debug exception (#DB) may occur when
a data breakpoint is set on a FP instruction
Errata (Sheet 3 of 4)
No.
C1/
0F0Ah
D0/
0F12h
B0/
0F24h
C1/
0F27h
D1/
0F29h
M0/
0F25h
L0/
0F29h
Plans Errata