Intel Xeon Processor MP Specification Update

Intel

Xeon

Processor MP Specification Update 7

Preface

Affected/Related Documents

This document is an update to the specifications contained in the following documents:

It is intended for hardware system manufacturers and software developers of applications,

operating systems, or tools. It contains Errata, Documentation Changes, Specification

Clarifications and Specification Changes.

Nomenclature

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their

unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the

processor identification information table. Care should be taken to read all notes associated with

each S-Spec number.

Errata are design defects or errors. Errata may cause the behavior of the Intel

Xeon

Processor

MP and Intel

Xeon

Processor MP with up to 4-MB L3 cache on 0.13- micron- micron process to

deviate from published specifications. Hardware and software designed to be used with any given

processor must assume that all errata documented for that processor are present on all devices

unless otherwise noted.

Documentation Changes include typos, errors, or omissions from the current published

specifications. These changes will be incorporated in the next release of the specifications.

Specification Clarifications describe a specification in greater detail or further highlight a

specification’s impact to a complex design situation. These clarifications will be incorporated in

the next release of the specifications.

Specification Changes are modifications to the current published specifications. These changes

will be incorporated in the next release of the specifications.

Document Title Document Number

Intel

Xeon™ Processor MP Datasheet 290740

Intel

Xeon™ Processor MP with up to 4MB L3 Cache (on 0.13 Micron Process)

Datasheet

251931

IA-32 Intel

Architecture Software Developer’s Manual, Volumes 1, 2A, 2B and 3 253665, 253666,

253667 and 253668,

respectively