Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 149
I/O Controller Hub 3 (Intel
®
ICH3-S)
9.5 Intel
®
ICH3-S SMBus/SMLink Interface
The SMBus interface on the ICH3-S uses two signals, SMBCLK and SMBDATA, to send and
receive data from components residing on the bus. These signals are used exclusively by the
SMBus host controller. The SMBus host controller resides inside the ICH3-S. If the SMBus is used
only for the SPD EEPROMs (one on each DIMM), both signals should be pulled up with a
4.7 k
Ω ± 5% resistor to VCC3_3.
The ICH3-S incorporates an SMLink interface supporting Alert on LAN*, Alert on LAN2*, and a
slave functionality. This interface uses two signals, SMLINK[1:0]. SMLINK0 corresponds to an
SMBus clock signal, and SMLINK1 corresponds to an SMBus data signal. These signals are part
of the SMBus Slave Interface.
For Alert on LAN* functionality, the ICH3-S transmits heartbeat and event messages over the
interface. When using the 82562EM Platform LAN Connect Component, the ICH3-S's integrated
LAN controller will claim the SMLink heartbeat and event messages and send them out over the
network. An external, Alert on LAN2-enabled LAN controller (i.e., Intel
®
82550) will connect to
the SMLink signals to receive heartbeat and event messages, as well as access the ICH3-S SMBus
Slave Interface. The slave interface function allows an external microcontroller to perform various
functions. For example, the slave write interface can reset or wake a system, generate SMI# or
interrupts, and send a message. The slave read interface can read the system power state, read the
watchdog timer status, and read system status bits.
Both the SMBus host controller and the SMBus Slave Interface obey the SMBus 2.0 protocol, so
the two interfaces can be externally wire-OR'd together to allow an external management ASIC
(e.g., 82550) to access targets on the SMBus as well as the ICH3-S Slave interface. Additionally,
the ICH3-S supports slave functionality, including the Host Notify protocol, on the SMLink pins.
This is done by connecting SMLink0 to SMBCLK and SMLink1 to SMBDATA.
Note: Intel does not support external access of the ICH3-S's Integrated LAN controller via the SMLink
interface. In addition, Intel does not support access of the ICH3-S's SMBus Slave Interface by the
ICH3-S's SMBus host controller. Refer to the Intel
®
82801CA I/O Controller Hub 3 (ICH3-S)
Datasheet for full functionality descriptions of the SMLink and SMBus interface.
Figure 9-6. Intel
®
ICH3-S SMBus / SMLink Interface
Intel
®
ICH3-S
Host Controller and
Slave Interface
SMBus
SMBCLK
SPD Data
Temperature on
Thermal Sensor
Network
Interface Card
on PCI
Microcontroller
Motherboard
LAN
Controller
Wire OR
(optional)
SMLink0
SMLink1
SMLink
SMBDATA