64-bit Intel Xeon Processor MP with up to 8MB L3 Cache Specification Update
64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 11
Summary Table of Changes
W= Intel
®
Celeron
®
M processor
X=Intel
®
Pentium
®
M processor on 90 nm process with 2 MB L2 cache
Y=Intel
®
Pentium
®
M processor
Z = Mobile Intel
®
Pentium
®
4 processor with 533 MHz system bus
AA= Intel
®
Pentium
®
processor Extreme Edition and Intel® Pentium® D processor on 65nm
process
AB = Intel
®
Pentium
®
4 processor on 65 nm process
AC = Intel
®
Celeron
®
processor in 478-pin package
AD= Intel
®
Celeron
®
D processor on 65nm process
AE = Intel
®
Core
TM
Duo Processor and Intel
®
CoreTM Solo processor on 65nm process
AF = Dual-Core Intel
®
Xeon
®
processor LV
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and other Intel
products do not use this convention.
Errata (Sheet 1 of 4)
No.
C-0/
0F41h
Plans ERRATA
U1 X No Fix Transaction is not retired after BINIT#
U2 X No Fix Invalid opcode 0FFFh requires A ModRM byte
U3 X No Fix Processor may hang due to speculative page walks to nonexistent system memory
U4 X No Fix Memory type of the load lock different from its corresponding store unlock
U5 X No Fix Machine check architecture error reporting and recovery may not work as expected
U6 X No Fix Debug mechanisms may not function as expected
U7 X No Fix Cascading of performance counters does not work correctly when forced overflow is enabled
U8 X No Fix EMON event counting of x87 loads may not work as expected
U9 X No Fix System bus interrupt messages without data and which receive a hard failure response may hang
the processor
U10 X No Fix The processor signals Page Fault exception (#PF) instead of Alignment Check exception (#AC) on
an unlocked CMPXCHG8B instruction
U11 X No Fix FSW may not be Completely Restored after Page Fault on FRSTOR or FLDENV instructions
U12 X No Fix Processor issues inconsistent transaction size attributes for locked operation
U13 X No Fix When the processor is in the System Management Mode (SMM), debug registers may be fully
writeable
U14 X No Fix Shutdown and IERR# may result due to a machine check exception on a HT Technology enabled
processor
U15 X No Fix Processor may hang under certain frequencies and 12.5% STPCLK# duty cycle
U16 X No Fix System may hang if a fatal cache error causes Bus Write Line (BWL) transaction to occur to the
same cache line address as an outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line
(BRIL)
U17 X No Fix A write to an APIC register sometimes may appear to have not occurred
U18 X No Fix Parity error in the L1 cache may cause the processor to hang
U19 X No Fix Sequence of locked operations can cause two threads to receive stale data and cause application
hang
U20 X No Fix Bus locks and SMC detection may cause the processor to temporarily hang
U21 X No Fix Incorrect debug exception (#DB) may occur when a data breakpoint is set on an FP instruction