64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

64-bit Intel

Xeon

Processor MP with up to 1 MB L2 Cache Specification Update 25

Errata

J28. Using STPCLK# and executing code from very slow memory could lead to a

system hang

Problem: The system may hang when the following conditions are met:

1. Periodic STPCLK# mechanism is enabled via the chipset

2. Hyper-Threading Technology is enabled

3. One logical processor is waiting for an event (i.e. hardware interrupt)

4. The other logical processor executes code from very slow memory such that every code fetch

is deferred long enough for the STPCLK# to be re-asserted.

Implication: If this erratum occurs, the processor will go into and out of the sleep state without making forward

progress, since the logical processor will not be able to service any pending event. This erratum has

not been observed in any commercial platform running commercial software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes.

J29. Processor provides a 4-Byte store unlock after an 8-Byte load lock

Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the

Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte

load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte

store unlock occurs. Correct data information is provided since only the lower bytes change,

however external logic monitoring the data transfer may be expecting an 8 byte load lock.

Implication: No known commercially available chipsets are affected by this erratum.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes.

J30. Machine check architecture error reporting and recovery may not work as

expected

Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the

situations described below, the processor does not report and/or recover from the error(s) as

intended.

When a transaction is deferred during the snoop phase and subsequently receives a Hard Failure

response, the transaction should be removed from the bus queue so that the processor may proceed.

Instead, the transaction is not properly removed from the bus queue, the bus queue is blocked, and

the processor will hang.

When a hardware prefetch results in an uncorrectable tag error in the L2 cache,

MC0_STATUS.UNCOR and MC0_STATUS.PCC are set but no Machine Check Exception (MCE)

is signaled. No data loss or corruption occurs because the data being prefetched have not been

used. If the data location with the uncorrectable tag error is subsequently accessed, an MCE will

occur. However, upon this MCE, or any other subsequent MCE, the information for that error will

not be logged because MC0_STATUS.UNCOR has already been set and the MCA status registers

will not contain information about the error which caused the MCE assertion, but instead will

contain information about the prefetch error event.

When the reporting of errors is disabled for Machine Check Architecture (MCA) Bank 2 by setting

all MC2_CTL register bits to 0, uncorrectable errors should be logged in the IA32_MC2_STATUS

which would normally be logged in the IA32_MC2_STATUS register, are not logged.