64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

24 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Errata
J24. Task Priority Register (TPR) Updates during voltage transitions of power
management events may cause a system hang
Problem: Systems with Echo TPR Disable (R/W) bit (bit [23] of IA32_MISC_ENABLE register) set to '0'
(default), where xTPR messages are being transmitted on the system bus to the processor, may
experience a system hang during voltage transitions caused by the power management events.
Implication: This may cause a system hang during voltage transitions of power management events.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. The BIOS workaround
disables the Echo TPR updates on affected steppings.
Status: For the steppings affected, see the Summary Table of Changes.
J25. Interactions between the instruction Translation Lookaside Buffer (ITLB)
and the instruction streaming buffer may cause unpredictable software
behavior
Problem: Complex interactions within the instruction fetch/decode unit may make it possible for the
processor to execute instructions from an internal streaming buffer containing stale or incorrect
information.
Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in
unpredictable software behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J26. Incorrect duty cycle is chosen when on-demand clock modulation is
enabled in a processor supporting Hyper-Threading Technology
Problem: When a processor supporting HT Technology enables On-Demand Clock Modulation on both
logical processors, the processor is expected to select the lowest duty cycle of the two potentially
different values. When one logical processor enters the AUTOHALT state, the duty cycle
implemented should be unaffected by the halted logical processor. Due to this erratum, the duty
cycle is incorrectly chosen to be the higher duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock Modulation is
enabled on both logical processors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J27. Memory aliasing of pages as uncacheable memory type and Write Back
(WB) may hang the system
Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB,
under certain bus and memory timing conditions, the system may loop in a continual sequence of
UC fetch, implicit writeback, and Request For Ownership (RFO) retries
Implication: This erratum has not been observed in any commercially available operating system or application.
The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as
being unsupported in the IA-32 Intel
®
Architecture Software Developer's Manual, Volume 3,
section 10.12.4, Programming the PAT. However, if this erratum occurs the system may hang
Workaround: The pages should not be mapped as either UC or WC and WB at the same time.
Status: For the steppings affected, see the Summary Table of Changes.