64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

22 64-bit Intel

Xeon

Processor MP with up to 1 MB L2 Cache Specification Update

Errata

J16. System may hang if a fatal cache error causes Bus Write Line (BWL)

transaction to occur to the same cache line address as an outstanding Bus

Read Line (BRL) or Bus Read-Invalidate Line (BRIL)

Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL

transaction to the same cache line address as an outstanding BRL or BRIL. As it is not typical

behavior for a single processor to have a BWL and a BRL/BRIL concurrently outstanding to the

same address, this may represent an unexpected scenario to system logic within the chipset.

Implication: The processor may not be able to fully execute the machine check handler in response to the fatal

cache error if system logic does not ensure forward progress on the System Bus under this scenario.

Workaround: System logic should ensure completion of the outstanding transactions. Note that during recovery

from a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL

transactions is not important. Forward progress is the primary requirement.

Status: For the steppings affected, see the Summary Table of Changes.

J17. A write to an APIC register sometimes may appear to have not occurred

Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC

interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register

(TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the

actual priority has been lowered. This may cause interrupts whose priority is lower than the initial

TPR, but higher than the final TPR, to not be serviced until the interrupt enabled flag is finally set,

i.e. by STI instruction. Interrupts will remain pending and are not lost.

Implication: In this example the processor may allow interrupts to be accepted but may delay their service.

Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC register

write. This will force the store to the APIC register before any subsequent instructions are

executed. No commercial operating system is known to be impacted by this erratum.

Status: For the steppings affected, see the Summary Table of Changes.

J18. Parity error in the L1 cache may cause the processor to hang

Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the

processor may hang while trying to evict the line.

Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any

commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes.

J19. Sequence of locked operations can cause two threads to receive stale data

and cause application hang

Problem: While going through a sequence of locked operations, it is possible for the two threads to receive

stale data. This is a violation of expected memory ordering rules and causes the application to

hang.

Implication: When this erratum occurs in an HT Technology enabled system, an application may hang.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Table of Changes.