Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2 Design Guidelines

Output Voltage Requirements
12 Voltage Regulator Module (VRM) and Enterprise Voltage
Regulator-Down (EVRD) 10.2 Design Guidelines
2.4 Stability - REQUIRED
The VRM/EVRD needs to be unconditionally stable under all specified output voltage ranges,
current transients of any duty cycle, and up to repetition rates of 1 MHz. The VRM/EVRD should
be stable under a no load condition.
2.5 Processor Power Sequencing - REQUIRED
The VRM/EVRD must support platforms with defined power-up sequences. Figure 2-3 shows a
block diagram of a system power-on sequencing implementation, and Figure 2-4 shows a timing
diagram of the power-on sequencing requirements.
Figure 2-3. Power-On Sequence Block Diagram
CPU
VCC
VID[5:0]
Vcc VRM/EVRD
Vtt VR
Vcc
VID[5:0]
Vcc_PW RGD
OUTEN
VTT
VTT
VID_PW RGOOD
VIDPW RGD
Delay
To System
PW RGD
Delay *
* This Delay could be built into the V
TT
VR