Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guidelines

VRM and EVRD 10.0 Design Guidelines
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2.3 Voltage Tolerance REQUIRED
The voltage ranges shown in Section 2.2 include the following tolerances:
• Initial DC output voltage set-point error
• Output ripple and noise
• No-load offset centering error
• Current sensing and droop errors
• Component aging effects
• Full ambient temperature range and warm up
• Dynamic output changes from minimum-to-maximum or maximum-to-minimum load, as
measured over a 20 MHz bandwidth
• Variations of the input voltage
2.4 Processor Vcc Overshoot REQUIRED
The Intel® Xeon™ processor with 800 MHz system bus processor and Low Voltage Intel®
Xeon™ processor with 800 MHz system bus can tolerate short transient overshoot events where
Vcc exceeds the VID voltage when transitioning from a high-to-low current load condition. This
overshoot cannot exceed VID + V
OS
_
MAX
. The overshoot duration, which is the time that the
overshoot can remain above VID, cannot exceed T
OS
_
MAX
. These specifications apply to the
processor socket voltage as measured across the remote sense points and should be taken with a
20 MHz bandwidth limited oscilloscope.
• V
OS
_
MAX
= Maximum overshoot voltage above VID = 50 mV
• T
OS
_
MAX
= Maximum overshoot time duration above VID = 25 µs
Figure 4. Vcc Overshoot Example Waveform
0 5 10 15 20 25
Time [us]
Voltage [V]
VID - 0.000
VID + 0.050
V
OS
T
OS
T
OS
: Overshoot time above VID
V
OS
: Overshoot voltage above VID