Intel Xeon Processor Multiprocessor Platform Design Guide

36
System Bus Routing
The following recommendations are Intel's best guidelines based on extensive simulation and
experimentation based on our reference platform. It is therefore strongly recommended to perform
a simulation analysis based on your platform.
Table 6-2 presents all signals interfacing with the processors. This table is included for reference
purposes only. Refer to the processor datasheet for current signal interfacing details.
NOTES:
1. These signals do not have on-die termination on the processor. They need to be terminated properly on the
motherboard. If they are not connected they will need to be pulled to the appropriate voltage level through a
1kΩ resistor.
2. These signals are “wired-OR” signals and may be driven simultaneously by multiple agents. For further
details on how to implement wired-OR signals refer to the routing guidelines in Section 6.4.1.5.
3. The value of these pins during the active to inactive edge of RESET# determine processor configuration
options.
4. SM_VCC is required for correct operation of the Intel Xeon processor MP with up to 2-MB L3 cache on the
0.13 micron process processor VID logic.
Table 6-2. System Bus Signals
Signal Group Type Signals
AGTL+ Common Clock Input Synchronous to BCLK
BPRI#, BR [3:1]#
1
, DEFER#, RESET#
1
, RS [2:0]#, RSP#,
TRDY#
AGTL+ Common Clock I/O Synchronous to BCLK
ADS#, AP[1:0]#, BINIT#
2
, BNR#
2
, BPM[5:0]#
1
, BR0#
1
,
DBSY#, DP[3:0]#, DRDY#, HIT#
2
, HITM#
2
, LOCK#,
MCERR#
2
AGTL+ Source Synchronous I/O:
4X Data Group
Synchronous to assoc. strobe D[63:0]#, DBI[3:0]#
AGTL+ Source Synchronous I/O:
2X Address Group
Synchronous to assoc. strobe A[35:3]#
3
, REQ[4:0]#
AGTL+ Strobes Synchronous to BCLK[1:0] ADSTB [1:0]#, DSTBN [3:0]#, DSTBP [3:0]#
Asynchronous GTL+ Input
1
Asynchronous
A20M#, IGNNE#, INIT#
3
, lint0/intr, lint1/ nmi, PWRGOOD,
SMI#
3
, SLP#, STPCLK#
Asynchronous GTL+ Output
1
Asynchronous FERR#, IERR#, THERMTRIP#, PROCHOT#
System Bus Clock Clock BCLK0, BCLK1
TAP Input
1
Synchronous to TCK tck, tdi, tms, trst#
TAP Output
1
Synchronous to TCK TDO
SMBus Interface
1
Synchronous to SM_CLK
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT, SM_CLK,
SM_ALERT#, SM_WP
Power/Other Power/Other
GTLREF[3:0], COMP[1:0], OTDEN, RESERVED,
SKTOCC#, TESTHI[6:0], VID[4:0], V
CC
, SM_VCC
4
, V
CCA
,
V
SSA
, V
CCIOPLL
, V
SS
, V
CCSENSE
, V
SSSENSE