Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

8 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
11.2.10 AGTL+ Reference Voltage ............................................................... 193
11.2.11 Component Models .......................................................................... 194
11.3 MCH Power Delivery Guidelines....................................................................... 195
11.3.1 DDR_VTT (1.25 V) Decoupling ........................................................ 195
11.3.2 VCC_CPU (1.50 V Power Plane) ..................................................... 195
11.3.3 DDR (2.5 V Power Plane) ................................................................ 195
11.3.4 Hub Interface (1.2 V Power Plane)................................................... 196
11.3.5 Filter Specifications (1.2 V Power Plane) ......................................... 196
11.3.6 MCH Power Sequencing Requirement ............................................ 198
11.4 Intel
®
ICH3-S Power Delivery Guidelines ......................................................... 199
11.4.1 1.8 V/3.3 V Power Sequencing ........................................................ 199
11.4.2 3.3 V/V5REF Sequencing ................................................................ 201
11.4.3 Intel
®
ICH3-S Power Rails ............................................................... 201
11.4.4 Intel
®
ICH3-S Decoupling Recommendations.................................. 202
11.5 Intel
®
P64H2 Power Requirements................................................................... 203
11.5.1 Intel
®
P64H2 Current Requirements ................................................ 203
11.5.2 Intel
®
P64H2 Decoupling Requirements ......................................... 203
11.5.3 PCIRST# Implementation................................................................. 204
11.5.4 Intel
®
P64H2 Power Sequencing Requirement................................ 204
12 High-Speed Design Concerns........................................................................... 205
12.1 Return Path ....................................................................................................... 205
12.2 Decoupling Theory ............................................................................................ 205
12.2.1 Bulk Decoupling ............................................................................... 206
12.2.2 High-Frequency Decoupling............................................................. 206
12.3 Serpentine Routing ........................................................................................... 207
12.4 EMI Design Considerations............................................................................... 208
12.4.1 Brief EMI Theory .............................................................................. 208
12.4.2 EMI Regulations and Certifications .................................................. 209
12.4.3 Spread Spectrum Clocking (SSC).................................................... 209
12.4.4 Differential Clocking ......................................................................... 210
12.4.5 PCI Bus Clock Control...................................................................... 211
12.4.6 EMI Test Capabilities ....................................................................... 211
12.5 Length Tuning ................................................................................................... 212
12.5.1 Signal to Strobe Flight Time Relationships ...................................... 213
12.5.2 Flight Time Segment Analysis.......................................................... 215
12.5.3 Length Tuning Equation Derivation .................................................. 216
12.5.4 DDR Example................................................................................... 217
12.5.5 Bus Length Tuning Methodology...................................................... 218
12.6 Processor Bus Tuning....................................................................................... 218
12.6.1 Compensating for Package Trace Length Differences..................... 218
12.6.2 Signal Integrity Adjustment Factor ................................................... 219
12.6.3 Final Length Matching Equation....................................................... 220
12.6.4 System Bus Length Matching Example............................................ 222
13 Schematic Checklist ............................................................................................. 225
13.1 Processor Schematic Checklist......................................................................... 225
13.2 MCH Schematic Checklist................................................................................. 229
13.3 Intel
®
ICH3-S Schematic Checklist ................................................................... 232
13.4 Intel
®
82870P2 P64H2 Schematic Checklist..................................................... 238