Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

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LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
SMB Address Resolution Protocol
SMB Address Resolution Protocol
SMB Address Resolution Protocol
SMB Address = A4h
ICH3_SMBUS_SEL0
ICH3_SMBUS_SEL1
ICH3_SMBCLK
GPIO28
GPIO27
SMBCLK
SMBDATA
ICH3_SMBDATA
SMB Address = A0h
SMB Address = A2h
P64H2 #2
SMB Address = C0h
PCI-X Slot 1
PCI-X Slot 2
P64H2 #1
SMB Address = C2h
This is actually the Read/Write bit, and may take on either value, depending on the nature of the transaction.
SMBus Addresses expressed as 8-bit hex numbers assume "0" as LSB.
NOTE:
MUX
SMB Address = A8h
SMB Address = AAh
SMB Address = ACh
CK-408B
SMB Address = D2h
I2C BUS 0
I2C BUS 2
I2C BUS 3
Partition Select 11 (Default)
Partition Select 10
I2C BUS 1
Partition Select 01
Partition Select 00
+V3_3
+V3_3
+V3_3
ICH3-S
SMB Slave Address = 88h
SMB Address = 60h
Processor 0 Thermal Sensor
SMB Address = 30h
SMB Address = 32h
Processor 1 Thermal Sensor
CPU1 IDROM = A2h
CPU0 IDROM = A0h
Power Supply
SMB Address = A6h
+VSBY5_0
PCI-X Slot 3
DIMM A-1
DIMM A-2
DIMM A-3
DIMM B-1
DIMM B-2
DIMM B-3
SMB Address = C8h
SMBUS PARTITION MAP
MCH
Gigabit LAN
8583
1.0INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD
11/18/02