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Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

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Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 195
Platform Power Delivery Guidelines
11.3 MCH Power Delivery Guidelines
The following guidelines are recommended for an optimal MCH power delivery. The main focus
of these guidelines is to minimize chipset power noise and signal integrity problems. The
guidelines are not intended to replace thorough system validation of products.
11.3.1 DDR_VTT (1.25 V) Decoupling
To reduce noise on the DDR termination voltage (1.25 V) around the MCH, two 0.1 µF and two
0.01 µF capacitors per-channel are recommended. Evenly distribute placement of decoupling
capacitors along the VTT plane around the MCH within 1 inch of the outer row of balls. Ceramic
0603 body type capacitors are recommended.
11.3.2 VCC_CPU (1.50 V Power Plane)
A maximum of five, 0.1 µF capacitors (minimum of four) are recommended (with 900 pH to
1.1 nH inductance) to be placed under the MCH for System Bus 1.50 V power plane decoupling.
The designer should evenly distribute placement of decoupling capacitors among the System Bus
interface signal field. In addition to the minimum decoupling capacitors under the MCH, the
designer should place a maximum of nine, evenly-spaced capacitors for the System Bus, at least
seven of which must be within 0.5 inch of the outer row of balls to the MCH.
11.3.3 DDR (2.5 V Power Plane)
A maximum of seven 0.1µF (minimum of five) capacitors are recommended (with 900 pH to
1.1 nH inductance) to be placed under the MCH for DDR 2.5 V power plane decoupling
(see Figure 11-19). The designer should evenly distribute placement of decoupling capacitors
among the DDR interface signal field. It is recommended that the designer use ceramic capacitor
0402 or 0805 body type. In addition to the minimum decoupling capacitors under the MCH, the
designer should place a maximum of 15, evenly-spaced capacitors for both DDR channels, and at
least 10 must be within 0.5 inch of the outer row of balls to the MCH.