Dual Intel Xeon Processor Voltage Regulator Down (VRD) Design Guidelines
Dual Intel
®
Xeon™ Processor Voltage Regulator Down (VRD) Guidelines
5
1 Scope
This document details the guidelines for developing a single embedded voltage regulator circuit
(VRD) to supply the required current and voltage to the common power plane for two Intel
®
Xeon™ processors or Low Voltage Intel Xeon Processors on a dual-processor-capable system
board. The parameters specified in this document are provided as guidelines only. For the most
current processor specifications please refer to the appropriate component datasheet.
Intel Xeon processors have unique requirements for voltages supplied to them. Their bus
implementation, called AGTL+, the processor core, and the cache are being powered from the
same voltage supply. Figure 1 shows two possible power distribution scheme options for the
system board designer:
Two plug-in voltage regulator modules (as defined in the VRM 9.0 or VRM 9.1 design
guidelines) operating in tandem with current-shared outputs and with one VRM per occupied
processor socket: that is, a 1:1 VRM-to-processor ratio
A single VRD, as detailed in this document.
Power
Supply
Voltage Regulator Module 1
(refer to VRM9.0/9.1)
Voltage Regulator Module 2
(refer to VRM9.0/9.1)
Intel® Xeon
TM
Processor
Intel Xeon Processor
Power
Supply
Voltage Regulator Down
Intel Xeon Processor
Intel Xeon Processor
Figure 1 – Power Distribution Options
This document does not address system boards supporting in excess of two processors (i.e.,
Multiple Processor or MP systems). Intel expects MP systems to use voltage regulator modules
(VRM 9.1), with a 1:1 VRM-to-processor ratio. The Dual Intel Xeon Processor VRD and
VRM 9.1 are electrically equivalent: a processor requires either implementation and its related
power delivery design to deliver the same voltage and current to the processor’s socket.
Figure 2 illustrates a basic electrical model for a single VRD, dual-processor power delivery
approach, based on an Intel Xeon processor – Intel 860 chipset platform core design.