Dual-Core Intel Xeon Processor 2.80 GHz Specification Update

22 Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update
Errata
Status: For the steppings affected, see the Summary Table of Changes.
D29. MOV CR3 performs incorrect reserved bit checking when in PAE paging
Problem: The MOV CR3 instruction should perform reserved bit checking on the upper unimplemented
address bits. This checking range should match the address width reported by CPUID instruction
0x8000008. This erratum applies whenever PAE is enabled.
Implication: Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail.
This erratum has not been observed with commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D30. Stores to page tables may not be visible to pagewalks for subsequent loads
without serializing or invalidating the page table entry
Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger
memory access may not get data from a programmatically older store to the page table entry if
there is not a fencing operation or page translation invalidate operation between the store and the
younger memory access. Refer to the IA-32 Intel
®
Architecture Software Developer’s Manual for
the correct way to update page tables. Software that conforms to the Software Developer's Manual
will operate correctly.
Implication: If the guidelines in the Software Developer's Manual are not followed, stale data may be loaded
into the processor's translation lookaside buffer (TLB) and used for memory operations. This
erratum has not been observed with any commercially available software.
Workaround: The guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual should be followed.
Status: For the steppings affected, see the Summary Table of Changes.
D31. Processor may fault when the upper 8 bytes of segment selector is loaded
from a far jump through a call gate via the local descriptor table
Problem: In IA-32e mode of the Intel
®
EM64T processor, control transfers through a call gate via the local
descriptor table (LDT) that uses a 16-byte descriptor, the upper 8-byte access may wrap and access
an incorrect descriptor in the LDT. This only occurs on an LDT with a LIMIT>0x10008 with a
16-byte descriptor that has a selector of 0xFFFC.
Implication: In the event this erratum occurs, the upper 8-byte access may wrap and access an incorrect
descriptor within the LDT, potentially resulting in a fault or system hang. Intel has not observed
this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D32. Loading a stack segment with a selector that references a non-canonical
address can lead to a #SS fault on a processor supporting Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack segment with a
selector which references a non-canonical address will result in a #SS fault instead of a #GP fault.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter unexpected behavior.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.