64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
22 Order Number: 302402-024
Errata 4
S1 Transaction is not retired after BINIT#
Problem: If the first transaction of a locked sequence receives a HITM# and DEFER#
during the snoop phase it should be retried and the locked sequence restarted.
However, if BINIT# is also asserted during this transaction, the transaction will
not be retried.
Implication: When this erratum occurs, locked transactions will not be retried.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S2 Invalid opcode 0FFFh requires a ModRM byte
Problem: Some invalid opcodes require a ModRM byte and other following bytes, while
others do not. The invalid opcode 0FFFh did not require a ModRM in previous
generation microprocessors such as Pentium II or Pentium III processors, but
it is required in the Intel Xeon processor.
Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a
page or limit fault on the Intel Xeon processor. When this erratum occurs,
locked transactions will not be retried.
Workaround:To avoid this erratum use ModRM byte with invalid 0FFFh opcode.
Status: For the steppings affected, see the Summary Table of Changes.
S3 Processor may hang due to speculative page walks to non-
existent system memory
Problem: A load operation issued speculatively by the processor that misses the data
translation lookaside buffer (DTLB) results in a page walk. A branch instruction
older than the load retires so that this load operation is now in the
mispredicted branch path. Due to an internal boundary condition, in some
instances the load is not canceled before the page walk is issued.
The page miss handler (PMH) starts a speculative page-walk for the Load and
issues a cacheable load of the page directory entry (PDE). This PDE load
returns data that points to a page table entry in uncacheable (UC) memory.
The PMH issues the PTE Load to UC space, which is issued on the front side
bus. No response comes back for this load PTE operation since the address is
pointing to system memory, which does not exist.
This load to non-existent system memory causes the processor to hang
because other bus requests are queued up behind this UC PTE load, which
never gets a response. If the load was accessing valid system memory, the
speculative page-walk would successfully complete and the processor would
continue to make forward progress.
Implication: Processor may hang due to speculative page walks to non-existent system
memory.