Voltage Regulator Module (VRM) 10.2L Design Guidelines

Output Voltage Requirements
14 Voltage Regulator Module (VRM) 10.2L Design Guidelines
Figure 2-6 is an example of dynamic VID. The diagram in Figure 2-6 assumes steady state,
constant current during the dynamic VID transition for ease of illustration; actual processor
behavior allows for any dIcc/dt during the transitions, depending on the code it is executing at that
time. Note that during dynamic VID, the processor will not output VID codes that would disable
the voltage regulator output voltage.
The processor load may not be sufficient to absorb all of the energy from the output capacitors on
the baseboard, when VID changes to a lower output voltage. The VRM design should ensure that
any energy transfer from the capacitors does not impair the operation of the VRM, the AC-DC
supply, or any other parts of the system.
Figure 2-5. Processor Transition States
VID High Load Line
1
2
3
4
Icc-max
5
VID Low Load Line
A
B
Figure 2-6. Dynamic VID Transition States Illustration
high VID to low VID
Vcc transition
450 mV
50 µs maximum settling
from registering final VID
450 mV
low VID to high VID
Vcc transition
The diagram assumes steady state, constant current during the dynamic VID
Transition for ease of illustration; actual processor behavior allows for any dIcc/dt
event during the transitions, depending on the code it is executing at that time
VID 5
36 VID steps @ 5 µs each step = 180 µs
Upper equals
Final VID-1.25mΩ*Icc
Lower equals
Start VID-1.25mΩ*Icc - 40mV
Maximum
Vcc
settling
Upper equals
Start VID-1.25mΩ∗Icc
Lower equals
Final VID-1.25mΩ*Icc - 40mV
50 µs maximum settling
from registering final VID
VID 4
VID 3
VID 2
VID 1
VID 0
400 ns
worst case VID
settling time