Intel Xeon Processor Specification Update

36 Intel
®
Xeon
®
Processor Specification Update
Errata
P27 Incorrect data may be returned when page tables are located in write
combining (WC) memory
Problem: If page directories and/or page tables are located in WC memory, speculative loads to cacheable
memory may complete with incorrect data.
Implication: Cacheable loads to memory mapped using page tables located in WC memory may return incorrect
data. Intel has not been able to reproduce this erratum with commercially available software.
Workaround: Do not place page directories and/or page tables in WC memory.
Status: For the steppings affected, see the Summary Table of Changes.
P28 FSW may not be completely restored after page-fault on FRSTOR or
FLDENV instructions
Problem: If the FPU operating environment or FPU state (operating environment and register stack) being
loaded by an FLDENV or FRSTOR instruction wraps around a 64-Kbyte or 4-Gbyte boundary and a
#PF or segment limit fault (#GP or #SS) occurs on the instruction near the wrap boundary, the
upper byte of the FPU status word (FSW) might not be restored. If the fault handler does not restart
program execution at the faulting instruction, stale data may exist in the FSW.
Implication: When this erratum occurs, stale data will exist in the FSW.
Workaround: Ensure that the FPU operating environment and FPU state do not cross 64-Kbyte or 4-Gbyte
boundaries. Alternately, ensure that the page-fault handler restarts program execution at the
faulting instruction after correcting the paging problem.
Status: For the steppings affected, see the Summary Table of Changes.
P29 Write combining (WC) load may result in an unintended address on system
bus
Problem: When the processor performs a speculative WC load, down the path of a mispredicted branch, and
the address happens to match a valid UC address translation with the DTLB, an unintended
UnCacheable load operation may be sent out on the system bus.
Implication: When this erratum occurs, an unintended load may be sent on system bus. Intel has only
encountered this erratum during pre-silicon simulation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum for some steppings of the
processor.
Status: For the steppings affected, see the Summary Table of Changes.
P30 Processor provides a 4-byte store unlock after an 8-byte load lock
Problem: When the processor is in the page address extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data is provided since only the lower bytes change, however external
logic monitoring the data transfer may be expecting an 8-byte store unlock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes