Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 45
Platform Clock Routing Guidelines
Platform Clock Routing Guidelines 4
To minimize jitter, improve routing, and reduce cost, E7500/E7501 chipset-based systems should
use a single chip clock solution, the CK408B. In this configuration, the CK408B provides four,
100 MHz or 133 MHz differential outputs pairs for all of the bus agents, including the ITP
connector, and five, 66 MHz speed clocks that drive all I/O buses. Figure 4-1 illustrates the clock
architecture for the platform. For more information on CK408B compliance, contact your Intel
representative.
Table 4-1. CK408B Clock Groups
Clock Group Name
Frequency
(MHz)
Receiver
Host_CLK 100 / 133 Processor 0, Processor 1, Debug Port, and MCH
CLK66 66 MCH, Intel
®
ICH3-S, and Intel
®
P64H2
CLK33_ICH3-S 33 ICH3-S
CLK14 14.318 ICH3-S and SIO
CLK33 33 PCI Connector, SIO, BMC, and FWH
USBCLK 48 ICH3-S