Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide
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LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
MBRA130
MBRA130
+V5_0
+V5_0
+V5_0
+V5_0
+V5_0
+V5_0
+V5_0
+V5_0
+V5_0
2N3904_DUAL
+V5_0
+V5_0
+V5_0
3
2
1
MBRA130
PGND
DSPS_DR
BG
DRN
TG
BST
GND
S_MOD
OVP_S
DELAY_C
CO
EN
PRDY
VCC
PGND
DSPS_DR
BG
DRN
TG
BST
GND
S_MOD
OVP_S
DELAY_C
CO
EN
PRDY
VCC
PGND
DSPS_DR
BG
DRN
TG
BST
GND
S_MOD
OVP_S
DELAY_C
CO
EN
PRDY
VCC
PGND
DSPS_DR
BG
DRN
TG
BST
GND
S_MOD
OVP_S
DELAY_C
CO
EN
PRDY
VCC
MBRA130
2N3904_DUAL
+VCC_CPU
HIP6311
PWM4
PGOOD
FS/DIS
PWM3
PWM2
PWM1
ISEN4
ISEN3
ISEN2
ISEN1
VCC
VSEN
VID4
VID3
VID2
VID1
VID0
FB
GND
COMP
+V5_0
3
2
1
3
2
1
Make GND
close to C2145
connection
CPU VOLTAGE REGULATOR DOWN(1 OF 2)
8572
3
2
1
Q118
R1562
2.67K
1%
C2177
100PF
NO POP
VR_130_HIP_COMP
R1581
10K
R1608
1K
NO POP
R1682
0
NO POP
R1568
44.2K
R1603
2.43K 1%
R1566
13.3K 1%
R1561
100
R1563
1.43K 1%
R1609
0
R1552
1
R1551
0
R1683
0
C2289
0.1UF
C2164
47PF
C2163
2700PF
R1570
5.1K 5%
VR_130A_PWM3
R1606
2.43K 1%
R1605
2.43K 1%
R1604 2.43K 1%
VR_130A_DRN4
72,73
VR_130A_DRN1
72,73
VR_130A_PWM1VRD_VID1
VRD_VID0
VRD_VID3
VRD_VID4
VRD_VID2
VRD_VID[4:0]74
VCC_CPU_SENSE
R1684
0
VR_130_HIP_FB
C2162
10UF
R1560
0
R16190
3
2
1
Q119
NO POP
DP_MODE
7,74
VR_130_HIP_B
VRD_OFF_N
74
ICH3_VRDPWRGD
63
VR130_EN
VR_130_PRDY4
R1582
1K
6
7
5
4
3
2
1
10
20
8
18
11
14
15
17
12
13
16
19
9
U158
C2156
10UF
3 6
5 2
4 1
Q88
C2171
10UF
C2169
10UF
C2167
10UF
C2165
0.047UF
VR_130A_BST4
VR_130A_BST3
VR_130A_BST2
VR_130A_BST1
12
CR51
10
11
9
12
13
14
3
5
1
6
4
2
7
8
U154
SC1405TS
10
11
9
12
13
14
3
5
1
6
4
2
7
8
U157
SC1405TS
10
11
9
12
13
14
3
5
1
6
4
2
7
8
U156
SC1405TS
10
11
9
12
13
14
3
5
1
6
4
2
7
8
U155
SC1405TS
12
CR50
3
2
1
Q120
R1558
1
R1556
1
R1554
1
VR_130A_DRN2
72,73
VR_130A_DRN3
72,73
VR_130A_DRN1_R
VR_130A_DRN2_R
VR_130A_DRN3_R
VR_130A_DRN4_R
VR_130A_TG2
VR_130A_BGATE2
73
VR_130A_BG4 VR_130A_BGATE4
73
VR_130A_DRN4
72,73
VR_130A_TGATE4
73
C2158
0.1UF
VR_130_SMOD
VR_130_DELAY3
VR_130_DELAY4
R1583
10K
R1580
1K
C2168
22PF
VR_130_RP_C_XSTR
VR_130_RP_XSTR
C2166
0.1UF
R1578
35.7K
R1577
10K
R1576
10K
R1575
10K
VR_130A_PWM2
VR_130A_PWM4
R1571
22
R1565
1K
R1564
10K
VR_130_CPU1_PRST
R1567
10K
VR_130_COMP_R_C
R1569
10K
R1559
10
R1572
22
R1573
22
R1574
22
3 6
5 2
4 1
Q89
R1584
1K
C2170
22PF
VR_130A_PWM4_CO
VR_130A_PWM3_CO
R1585
1K
C2172
22PF
VR_130_DELAY2
VR_130A_PWM2_CO
R1550
1K
C2157
22PF
VR_130_DELAY1
VR_130A_PWM1_CO
VR_130A_TG4
C2159
0.1UF
R1553
0
VR_130A_BG3 VR_130A_BGATE3
73
VR_130A_DRN3
72,73
VR_130A_TGATE3
73
VR_130A_TG3
C2160
0.1UF
R1555
0
VR_130A_BG2
VR_130A_DRN2
72,73
VR_130A_TGATE2
73
C2161
0.1UF
R1557
0
VR_130A_BG1 VR_130A_BGATE1
73
VR_130A_DRN1
72,73
VR_130A_TGATE1
73
VR_130A_TG1
12
CR48
12
CR49
VR_130_XSTR_FET
1.0INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD
11/18/02