Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

+V1_8_ICH3
+V1_8_ICH3
+V3_3
+V3_3
+V3_3
A20GATE
A20M_N
AD0
AD1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD2
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD3
AD30
AD31
AD4
AD5
AD6
AD7
AD8
AD9
APICCLK
APICD0
APICD1
CBE0_N
CBE1_N
CBE2_N
CBE3_N
CPUPWRGD
CPUSLP_N
DEVSEL_N
NC6
EE_CS
EE_DIN
EE_DOUT
EE_SHCLK
FERR_N
FRAME_N
GNT0_N
GNT1_N
GNT2_N
GNT3_N
GNT4_N
GNT5_M_GNTB_N_GPIO17
GNTA_N_GPIO16
HI0
HI1
HI10
HI11
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HICOMP
HIREF
HITERM
IGNNE_N
INIT_N
INTR
IRDY_N
IRQ14
IRQ15
LANCLK
LANRSTSYNC
LANRXD0
LANRXD1
LANRXD2
LANTXD0
LANTXD1
LANTXD2
NMI
PAR
PCICLK
PCIRST_N
PERR_N
PIRQA_N
PIRQB_N
PIRQC_N
PIRQD_N
PIRQE_GPIO2
PIRQF_GPIO3
PIRQG_GPIO4
PIRQH_GPIO5
PLOCK_N
PME_N
RCIN_N
REQ0_N
REQ1_N
REQ2_N
REQ3_N
REQ4_N
REQ5_N_REQB_N_GPIO1
REQA_N_GPIO0
SERIRQ
SERR_N
SMI_N
STOP_N
STPCLK_N
TRDY_N
HI_STBS
HI_STBF
INTERRUPT INTERFACEI/F
EEPROM
LAN INTERFACE
PCI INTERFACE
HUB INTERFACE
ICH3 (PART 1 0F 4)
CPU INTERFACE
2N3904_DUAL
74LVC125
R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
74LVC125
Voltage translation on FERR# is not
required if +VCC_CPU is greater than 1.3V.
Place these
ICH3-S (Part 1)
caps near the pins
Place these caps
near the pins
61 85
R630 8.2K 8.2K R629
R635
56
R631 8.2K
ICH3_PCIRST_N
61,64,65,66
PCIRST_2_N
27,31,68,69
4
5 6
U69
1%825
R628
C863
0.1UF 0.01UF
C637
C638
0.01UF 0.1UF
C862
R672 78.7 1%
ICH3_HITERM
R627 261 1%
R633 261 1%
INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD 1.0
11/18/02
1
2 3
U69
3 6
5 2
4 1
Q19
PCIRST2_5_N
11,16,17,18,21,22,23
CPU_STPCLK_N
4,6,9
R1087
0
CPU_LINT1_NMI
4,6,9
R636
10K
R632
470
CPU_FERR_N
4,6
Y22
J2
K1
L4
H4
M4
J3
M5
J1
F5
N2
G4
P2
J4
G1
P1
F2
P3
F3
R1
E2
N4
D1
P4
K3
E1
P5
H5
K4
H3
L1
L2
G2
J19
J20
J21
W23
E9
D8
E8
D10
L22
M21
N19
R19
M23
N20
P21
R22
R20
T23
M19
P19
N22
AA23
AB14
W19
C9
D7
C8
A8
A9
B9
C10
A10
Y21
G5
T5
A6
B5
C5
A5
H22
K2
K5
N1
R2
M3
F1
N3
H1
H2
M2
Y1
M1
L5
W1
C4
D4
B6
B3
D3
F4
A3
R4
E4
A4
E3
D2
D5
B4
A2
B2
C1
B1
P23
AB22
U22
U23
Y23
AB23
AA21
J22
W21
V23
K19
L20
L19
U63
10K
R670
SIO_PME_N
69
ICH3_LAN_CLK
R671
10K
R669
10K
ICH3_PSTRBF
11
ICH3_PSTRBS
11
ICH3_FERR_N
470
R1062
ICH3_A20GATE
69
ICH3_APICD0
ICH3_IRQ15
ICH3_PCIRST_N
61,64,65,66
ICH3_CLK33
80
ICH3_SERIRQ
69
ICH3_RCIN_N
69
ICH3_HI0
ICH3_HI[11:0]
11
ICH3_HI11
ICH3_HI10
ICH3_HI9
ICH3_HI8
ICH3_HI7
ICH3_HI6
ICH3_HI5
ICH3_HI4
ICH3_HI3
ICH3_HI2
ICH3_HI1
ICH3_HICOMP
ICH3_PIRQF_GPIO3
65
ICH3_PIRQH_GPIO5
65
ICH3_CPUPWRGD
4,6
ICH3_PIRQD_N
65
ICH3_PIRQC_N
65
ICH3_PIRQB_N
31,65
ICH3_PIRQA_N
27,65,66
ICH3_REQ3_N
65
ICH3_REQ0_N
65
ICH3_GNT0_N
65
ICH3_SERR_N
65,66
ICH3_PME_N
36,42,43,60,65
ICH3_PLOCK_N
65
ICH3_PERR_N
65
ICH3_PAR
65,66
ICH3_STOP_N
65,66
ICH3_TRDY_N
65,66
ICH3_FRAME_N
65,66
ICH3_CBE3_N
65,66
ICH3_IRDY_N
65,66
ICH3_DEVSEL_N
65,66
65,66 ICH3_CBE2_N
ICH3_AD[31:0]
65,66
ICH3_AD31
ICH3_AD30
ICH3_AD29
ICH3_AD28
ICH3_AD27
ICH3_AD26
ICH3_AD25
ICH3_AD24
ICH3_AD23
ICH3_AD22
ICH3_AD21
ICH3_AD20
ICH3_AD19
ICH3_AD18
ICH3_AD17
ICH3_AD16
ICH3_AD15
ICH3_AD14
ICH3_AD13
ICH3_AD12
ICH3_AD11
ICH3_AD10
ICH3_AD9
ICH3_AD8
ICH3_AD7
ICH3_AD6
ICH3_AD5
ICH3_AD4
ICH3_AD3
ICH3_AD2
ICH3_AD1
ICH3_AD0
ICH3_PIRQE_GPIO2
65
ICH3_PIRQG_GPIO4
65
ICH3_GNT5_GNTB_N
ICH3_GNT4_N
ICH3_GNT3_N
ICH3_GNT2_N
ICH3_GNT1_N
ICH3_REQ4_N
65
ICH3_REQ2_N
65
ICH3_REQ1_N
65
ICH3_GNTA_N
64
ICH3_A20M_N
4,6,9
ICH3_CPUSLP_N
4,6,9
ICH3_IGNNE_N
4,6,9
ICH3_INIT_N
4,6,9,68
ICH3_LINT0_INTR
4,6,9
ICH3_SMI_N
4,6,9
ICH3_IRQ14
64
ICH3_APICCLK
ICH3_EE_SHCLK
ICH3_EE_DIN
ICH3_EE_DOUT
ICH3_EE_CS
ICH3_LAN_RXD0
ICH3_LAN_RXD1
ICH3_LAN_RXD2
ICH3_LANRSTSYNC
ICH3_LAN_TXD0
ICH3_LAN_TXD1
ICH3_LAN_TXD2
65,66
ICH3_CBE1_N
65,66
ICH3_CBE0_N
ICH3_APICD1
LPC_SMI_N
69
ICH3_PCIRST_N
61,64,65,66
ICH3_HIREF