Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

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Introduction

26 Intel

Xeon™ Processor and Intel

E7500/E7501 Chipset Compatible Platform Design Guide

1.3.3 Peak Bandwidth Summary

Table 1-5 describes the clock maximum speed, sample rate, and peak bandwidth for each of the

interfaces in the E7500/E7501 chipset based platform.

1.3.4 System Configurations

Figure 1-1 illustrates an example E7500/E7501 chipset-based system configuration for server

platforms using Intel Xeon processors.

Table 1-5. Platform Peak Bandwidth Summary

Interface

Clock Speed

(MHz)

Samples per

Clock

Data Width

(Bytes)

Peak Bandwidth

(MB/s)

System Bus (Data) 100 / 133 4 8 3200 / 4270

DDR Interface 100 / 133 2 16 3200 / 4270

Hub Interface_A 66 4 1 266

Hub Interface_B,C,D 66 8 2 1066

PCI-X 133 1 8 1066

Figure 1-1. Example Intel

E7500/E7501 Chipset-Based System Configuration

Intel

ICH3-S

MCH

USB 1.1, 6 Ports

AC '97

Codec(s)

AC'97 2.1

1–4 FWHs

10/100 LAN

Controller

4 IDE Devices

UltraATA/100

System Memory

GPIOs

ProcessorProcessor

SMBus 2.0

SMBus

Devices

LPC I/F

Super I/O

PCI Bus

PCI

Slots

PCI

Agent

Intel®

P64H2

PCI / PCI-X

Hot Plug

16-bit

HI 2.0

P64H2

PCI / PCI-X

Hot Plug

16-bit

HI 2.0

DDR-200 or

DDR-266

DDR-200 or

DDR-266

P64H2

PCI / PCI-X

Hot Plug

16-bit

HI 2.0

8-bit

HI 1.5