Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

High-Speed Design Concerns
224 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
Part 2 Solution: By definition, the DSTBN0# signal 4-inch route already includes the PLC and SI
motherboard trace components. The SI value can be used from Part 1. The MCH PLC values are
determined for DSTBN0# and DSTBP0# using Equation 12-3.
DSTBN0#
MCH PLC
= Maximum in Group
MCH Package Length
- DSTBN0#
MCH Package Length
= 1.060 inch - 0.842 inch = 0.218 inch
DSTBP0#
MCH PLC
= Maximum in Group
MCH Package Length
- DSTBP0#
MCH Package Length
= 1.060 inches - 0.738 inch = 0.322 inch
The DSTBP0# Processor 1/MCH motherboard lengths are calculated using Equation 12-11.
DSTBP0#
Processor 1 to MCH PCB Length
= DSTBN0#
Processor 1 to MCH PCB Length
“
–DSTBN0#
MCH PLC
– DSTBN0#
SI Adj
+ DSTBP0#
MCH PLC
+ DSTBP0#
SI Adj
= 4.000 – 0.218 – 0.289 + 0.322 + 0.346 = 4.161 inches
Since the system bus data signals must be length matched within ± 25 mils between components,
the DSTBP0# Processor 1/MCH motherboard length is 4.161 ± 0.025 inch.
The above example demonstrates the importance of the first routed motherboard traces since these
will establish the routing lengths for the remaining signals in the same signal group. Therefore, the
DSTBP0#
Processor 0 to Processor 1 PCB Length
and DSTBP0#
Processor 1 to MCH PCB Length
values
should be chosen carefully based on routing studies to avoid multiple iterations of length matching
computations for each signal.