64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
48 Order Number: 302402-024
instructions are supported and able to be executed without an Invalid Opcode
exception.
Implication: The CPUID feature flag incorrectly reports LAHF/SAHF instructions as
unavailable in 64-bit mode, though they can be executed normally.
Workaround:It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S90 IRET under certain conditions may cause an unexpected
Alignment Check Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on
the IRET instruction even though alignment checks were disabled at the start
of the IRET. This can only occur if the IRET instruction is returning from CPL3
code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can
occur if the EFLAGS value on the stack has the AC flag set, and the interrupt
handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte
boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC
even if alignment checks are disabled at the start of the IRET. This erratum
can only be observed with a software generated stack frame.
Workaround:Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Table of Changes.
S91 Upper 32 bits of ‘From’ address reported through LBR or LER
MSRs, BTMs or BTSs may be incorrect
Problem: When a far transfer switches the processor from IA-32e mode to 32-bit mode,
the upper 32 bits of the ‘From’ (source) addresses reported through the LBR
(Last Branch Record) or LER (Last Exception Record) MSRs (Model-Specific
Registers), BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may
be incorrect.
Implication: The upper 32 bits of the ‘From’ address debug information reported through
LBR or LER MSRs, BTMs or BTSs may be incorrect.
Workaround:It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S92 EXTEST/CLAMP may cause incorrect values to be driven on
processor pins
Problem: When using TAP boundary scan instructions EXTEST/CLAMP while SLP# is
asserted at certain bus ratios, incorrect values may be driven on some
processor pins. Address Strobe pins do not respond at bus ratios 15:1 and
16:1, while Address pins and Request Command pins do not respond at bus
ratio 22:1 and 24:1.
Implication: Due to this erratum, incorrect values may be driven on some processor pins
during boundary scan testing.
Workaround:Avoid asserting SLP# when using TAP Boundary Scan instructions EXTEST/
CLAMP.
Status: For the steppings affected, see the Summary Table of Changes.