64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
40 Order Number: 302402-024
Implication: No impact to properly written code since both types of faults will be generated
but in the opposite order.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S63 Writes to IA32_MISC_ENABLE may not update flags for both
logical processors
Problem: On processors supporting HT Technology with Execute Disable Bit feature,
writes to IA32_MISC_ENABLE may only update IA32_EFER.NXE for the current
logical processor.
Implication: Due to this erratum, the non-current logical processor may not update its
IA32_EFER.NXE bit.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S64 Execute Disable Bit set with CR4.PAE may cause livelock
Problem: If the Execute Disable bit of IA32_MISC_Enable is set along with the PAE bit of
CR4 (IA32_EFER.NXE & CR4.PAE), the processor may livelock.
Implication: When this erratum occurs, the processor may livelock resulting in a system
hang or operating system failure.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S65 SYSENTER or SYSEXIT instructions may experience incorrect
canonical address checking on processors supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: Processors which support Intel EM64T always perform canonical address
checks before accessing memory. SYSENTER or SYSEXIT instructions may
check an incorrect address.
Implication: Due to this erratum, an unexpected #GP fault may occur, or a reference to a
non-canonical address without a #GP fault may occur.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S66 Checking of Page Table Base Address may not match Address
Bit Width supported by the platform
Problem: If the page table base address included in the page map level-4 table, page-
directory pointer table, page-directory table, or page table exceeds the
physical address range supported by the platform (e.g. 36 bits) and it is less
than the implemented address range (e.g. 40 bits), the processor does not
check to see if the address is invalid.
Implication: If software sets such an invalid physical address in the listed tables, the
processor does not generate a page fault (#PF) upon accessing that virtual
address, and the access results in an incorrect read or write. If BIOS provides
only valid physical address ranges to the operating system, this erratum will
not occur.