64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update
Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
38 Order Number: 302402-024
Workaround:None identified.
Status: For the steppings affected, see the Summary Table of Changes.
S54 Loading a stack segment with a selector that references a non-
canonical address can lead to a #SS fault on a processor
supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack
segment with a selector which references a non-canonical address will result in
a #SS fault instead of a #GP fault.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter
unexpected behavior.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S55 CPUID instruction incorrectly reports CMPXCH16B as supported
Problem: A read of the CMPXCHG16B feature flag improperly indicates that the
CMPXCHG16B instruction is supported.
Implication: When a processor supporting Intel EM64T attempts to execute a CMPXCH16B
instruction, the system may hang rather than #UD fault.
Workaround:It is possible for the BIOS to contain a workaround for this erratum, such that
the CMPXCH16B feature flag indicates that the instruction is not supported, and
the execution of the CMPXCHG16B instruction results in a #UD fault.
Status: For the steppings affected, see the Summary Table of Changes.
S56 FXRSTOR may not restore non-canonical effective addresses on
processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) enabled
Problem: If an x87 data instruction has been executed with a non-canonical effective
address, FXSAVE may store that non-canonical FP Data Pointer (FDP) value
into the save image. An FXRSTOR instruction executed with 64-bit operand size
may signal a General Protection Fault (#GP) if the FDP or FP Instruction
Pointer (FIP) is in non-canonical form.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an
unintended #GP fault.
Workaround:Software should avoid using non-canonical effective addressing in EM64T
enabled processors. BIOS can contain a workaround for this erratum removing
the unintended #GP fault on FXRSTOR.
Status: For the steppings affected, see the Summary Table of Changes.
S57 A push of ESP that faults may zero the upper 32-bits of RSP
Problem: In the event that a push ESP instruction, that faults, is executed in
compatibility mode, the processor will incorrectly zero upper 32-bits of RSP.
Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to
this erratum, this instruction fault may change the contents of RSP. This
erratum has not been observed in commercially available software.
Workaround:None at this time.