64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

38 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Errata
• The shared data is aligned.
• Proper semaphores or barriers are used in order to prevent concurrent data accesses.
Status: No Fix
J75. Processor may hang during entry into No-Fill Mode or No-Eviction Mode.
Problem: Only one logical processor per core can be active when processor is put in No-Fill Mode or
No-Eviction Mode. If the other logical processor is active or there is an internal or external event
pending to wake that logical processor, the processor may hang when writing to MSR
IA32_BIOS_CACHE_AS_RAM (80H).
Implication: A processor may hang due to this erratum. Intel has not observed this erratum with any
commercially available software or system.
Workaround: None identified.
Status: No Fix
J76. FPU Operand pointer may not be cleared following FINIT/FNINIT.
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87 FPU
Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector (both fields form
the FPUDataPointer). Saving the floating point environment with FSTENV, FNSTENV, or
floating point state with FSAVE, FNSAVE or FXSAVE before an intervening FP instruction may
save uninitialized values for the FPUDataPointer.
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point image or
floating point environment structure may appear to be random values. Executing any non-control
FP instruction with memory operand will initialize the FPUDataPointer. Intel has not observed this
erratum with any commercially available software.
Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or floating point
environment saved memory image to be correct, until at least one non-control FP instruction with a
memory operand has been executed.
Status: No Fix
J77. L2 Cache ECC machine-check errors may be erroneously reported after an
asynchronous RESET# assertion.
Problem: Machine check status MSRs may incorrectly report the following L2 Cache ECC machine-check
errors when cache transactions are in-flight and RESET# is asserted:
• Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153).
• L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145).
Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported. Intel has not
observed this erratum on any commercially available system.
Workaround: When a real run-time L2 Cache ECC Machine Check occurs, a corresponding valid error will
normally be logged in the IA32_MC0_STATUS register. BIOS may clear IA32_MC2_STATUS
and/or IA32_MC1_STATUS for these specific errors when IA32_MC0_STATUS does not have its
VAL flag set.
Status: No Fix