Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 27
Errata
Implication: The L1 cache may contain corrupted data. No known commercially available chipsets trigger the
failure conditions.
Workaround: The chipset could issue a BIL (snoop) to the deferred processor to eliminate the failure conditions.
Status: For the steppings effected, see the Summary Table of Changes.
O22 The processor signals page-fault exception (#PF) instead of alignment
check exception (#AC) on an unlocked CMPXCHG8B instruction
Problem: If a page-fault exception (#PF) and alignment check exception (#AC) both occur for an unlocked
CMPXCHG8B instruction, then #PF will be flagged.
Implication: Software that depends on #AC before the #PF will be affected since #PF is signaled in this case.
Workaround: Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the
page-fault in the page-fault handler and then restart the faulting instruction.
Status: For the steppings effected, see the Summary Table of Changes.
O23 Incorrect data may be returned when page tables are located in write
combining (WC) memory
Problem: If page directories and/or page tables are located in WC memory, speculative loads to cacheable
memory may complete with incorrect data.
Implication: Cacheable loads to memory mapped using page tables located in WC memory may return incorrect
data. Intel has not been able to reproduce this erratum with commercially available software.
Workaround: Do not place page directories and/or page tables in WC memory.
Status: For the steppings effected, see the Summary Table of Changes.
O24 Multiprocessor boot protocol may not complete with an IOQ depth of one
Problem: When the in-order queue (IOQ) depth is managed by the chipset to be one entry deep, the system
may hang during the multi-processor boot protocol. This hang occurs when the chipset drives
BNR# in such a way that the processors are continually throttled off the bus then released to access
the bus in alternating cycles which never allows the multi-processor boot protocol to complete
execution.
Implication: The system may hang during the multiprocessor boot protocol.
Workaround: If the chipset drives BNR# in such a way that the processors are continually throttled off the bus
then released to access the bus in alternating cycles, do not use IOQ de-pipelining.
Status: For the steppings effected, see the Summary Table of Changes.
O25 Write combining (WC) load may result in an unintended address on system
bus
Problem: When the processor performs a speculative WC load, down the path of a mispredicted branch, and
the address happens to match a valid UC address translation with the DTLB, an unintended UC
load operation may be sent out on the system bus.
Implication: When this erratum occurs, an unintended load may be sent on the system bus. Intel has only
encountered this erratum during pre-silicon simulation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum for some steppings of the
processor.
Status: For the steppings effected, see the Summary Table of Changes.