ITP700 Debug Port Design Guide

15 Appendix F – ITP700 DPA Spice

Models

Intel has a behavioral spice model of the ITP hardware available for simulation of critical routes

and topography. Intel strongly recommends that these models be used to simulate at the very least,

TCK, BCLK and Execution signal integrity and timing.

The models are created and packaged as single signal models. Each model contains a

representation of all passive components on the ITP hardware between the debug port pins to the

driver or receiver pin on the ITP (Including a model of the mated debug port Header). The heading

of each model documents the input and output path of the circuit and where the model of the driver

or receiver is to be located for a full simulation. It is not legal for Intel to package spice models of

the actual driver or receiver component with the ITP spice models. The companies that produce

these components will have to be contacted directly to obtain these models. A spice model for the

VCX16374 is available from Toshiba. A spice model for the QS3125 is available from Quality

Semiconductor. Spice models for MC100LVEL17 are available from Motorola. See Motorola

Application Note AN1560 for further information on how to use these models.

The ITP models were originally created in VBASE*, a Mentor Graphics analog simulation

language. The models are fully compatible with P-SPICE and H_SPICE. Any issues with VBASE

may be directed to Mentor Graphics for assistance. The following is a list of models that are

available for the ITP hardware.

Drive Pins:

***************************************************

* TCKDR

* TCK DRIVE MODEL LEVEL 1

* UPDATED: NOVEMBER 18, 1998

* EXPANDED DOCUMENTATION: AUGUST 18, 2000

* PINS:

* GNDREF=GROUND

* DRV=DRIVE FROM SEVEN VCX OUTPUTS,

* M2=MINITEK* CONNECTOR AT TARGET

* ADDITIONAL REQUIRED SUBCIRCUITS INCLUDED IN PACKAGES.TXT:

* QSOP = QSOP PIN MODEL, PACKAGE APPROXIMATION